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2024-09-11tree: Use boolean for dmi_power_optimize_disableElyes Haouas
Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11tree: use boolean for hybrid_storage_modeElyes Haouas
Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-28tree: Use boolean for "eist_enable"Elyes Haouas
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-08-06mb/msi/ms7d25,ms7e06: Enable discrete TPM module supportMichał Żygowski
Now that multiple TPM drivers may be compiled in, it is possible to support switching between fTPM and dTPM. The patch adds: - Device tree entry for PC80 discrete TPM - TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt - MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver When the ME is disabled, e.g. via HECI command, chipset will route the TPM traffic to SPI automatically. When a SPI TPM is connected to the JTPM1 on the board, it will be probed successfully and initialized in place of inactive PTT/fTPM. Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-09-01mb/msi/ms7d25: Configure ASPM and Clock PM based on KconfigMichał Żygowski
Add support for FSP ASPM and Clock PM configuration based on Kconfig options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some use cases it may be desirable to disable ASPM and Clock PM to achieve more deterministic and higher performance of PCIe devices. TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all PCIe devices are still working and ASPM and Clock PM capabilities are not present on the PCIe Root Ports. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/msi/ms7d25: Re-enable GpioOverrideMichał Żygowski
Set all GPIOs to their target functions and do not depend on FSP to configure them. The board support has stabilized and was tested with many PCIe devices. There is no need to detect CLKREQ signals so we may hardcode them. TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock PM features' state on PCIe root ports are the same before and after the change. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I01dc83ce23ca27525b8905665da942510f249824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22mb/msi/ms7d25: Disable PCIe hotplugMichał Żygowski
The support for the board has stabilized and PCIe ports have been tested with many devices. Although hotplug is not commonly used and it seems pointless to keep it enabled, so disable it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I338c55cb57d971badd08235b71626a710fafb829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/msi/ms7d25: Update USB port macrosMichał Żygowski
Update USB port macros: - change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1, HUB to USB 2.0 headers, HUB to rear USB 2.0 - change USB type C header to LONG which caused hard lockups on the port making it unable to enumerate in UEFI Payload and Linux - add empty definitions for USBr ports Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-26mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2022-07-11mb/msi/ms7d25: Properly handle CnvDdrRfim parameterMichał Żygowski
CNVi DDR RFIM feature should be reported via _DSM function. Add the generic WiFi device which will generate the proper ACPI code and pass the CnviDdrRfim parameter to FSP by SoC driver. TEST=Connect to WiFi network on Ubuntu. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice2abe972f38dd819f7f0103f7b9a697096f1cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63835 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add USB macros and port designation commentsMichał Żygowski
Add the comments about port designation after mapping the root hub ports to board connectors. Add macros reflecting the length of the USB signal traces. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib2e842ef240ab25e2a9f7fa2e0766206fde7943d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-11mainboard/msi/ms7d25: Add FIVR configurationMichał Żygowski
Reflect the vendor's firmware FIVR settings. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I97b3b4f9470267961c138fea70703606373f6d52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64051 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add NCT6687D configurationMichał Żygowski
TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors to display information about sensors on the SIO EC. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I55445a94f0de3510324b12558c4343e819412ac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Enable PTTMichał Żygowski
Original firmware ships with PTT enabled by default on poweron. PTT takes priority over SPI/LPC TPM so enable the CRB interface until coreboot implements a way to select the interface and adapt the API to handle any TPM detection. TEST=Boot the board and see PTT is detected by Windows and Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/msi/ms7d25: Configure HD AudioMichał Żygowski
Apply correct configuration of HD Audio. TEST=Launch ubuntu 20.04 and launch a YouTube video, check if microphone detects an input in the system sound settings. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6acc22aa58f6cc99df1d48d651122e74fe08ec02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63723 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/msi/ms7d25: Configure PCIe Root PortsMichał Żygowski
Add the full PCIe root port configuration. Proper initialization of the root ports depends on the correct GPIO programming including virtual wires. Do not program the CLKREQ signals in coreboot to let FSP detect and configure CLKREQ pads. Otherwise the CLKREQ pads are reprogrammed by FSP despite having GpioOverride=1. The pads that should not be touched by coreboot are left commented in the board GPIO file. CLKREQ reprogramming caused undefined behavior when ASPM and Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed a lot of exceptions and simply halted). TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots populated and check if they are detected and functional in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08mb/msi/ms7d25: Enable displaysMichał Żygowski
Add VBT from vendor firmware v5.24 and configure display outputs in devicetree. TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the connected display via HDMI or DisplayPort on rear panel. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mb/msi/ms7d25: add basic FSP configuration in devicetreeMichał Kopeć
Configure some basic FSP parameters in devicetree for to allow for booting an OS. Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63499 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFIMichał Żygowski
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 04:53:50 +0000