| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-26 | mb/lowrisc: Remove the Nexys4DDR port | Jonathan Neuschäfer |
| 2018-06-09 | mainboard: Get rid of device_t in ramstage | Elyes HAOUAS |
| 2018-06-02 | src/mainboard: Add and update license headers | Martin Roth |
| 2018-04-27 | RISC-V boards: Remove PAGETABLES section from memlayout.ld | Jonathan Neuschäfer |
| 2017-11-07 | RISC-V boards: Stop using the config string | Jonathan Neuschäfer |
| 2016-12-06 | mb/lowrisc/nexys4ddr: Read RAM information from the config string | Jonathan Neuschäfer |
| 2016-12-06 | mb/lowrisc/nexys4ddr: Initialize CBMEM in romstage | Jonathan Neuschäfer |
| 2016-11-07 | riscv: Unify SBI call implementations under arch/riscv/ | Jonathan Neuschäfer |
| 2016-11-07 | mb/lowrisc/nexys4ddr: Actually fix the UART clock setup | Jonathan Neuschäfer |
| 2016-10-28 | riscv: add the lowrisc/nexys4ddr mainboard | Ronald G. Minnich |
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index : coreboot.git | |
| my copy of coreboot | User & |
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