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This board doesn't support the newest RISC-V Privileged Architecture
spec (1.10), and it's based on an FPGA so it's a moving target.
Now that there's actual RISC-V silicon out there (from SiFive),
mb/lowrisc/nexys4ddr will only continue to bitrot.
Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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RISC-V doesn't set up page tables anymore, since commit b26759d703
("arch/riscv: Don't set up virtual memory").
Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This was tested at the coreboot meeting in Berlin.
The uart programming may still not be right but when used with
the lowrisc bitstream for the board we were able to load
and start linux, although it does not yet get far due to
PTE version issues with lowrisc.
Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17132
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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