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Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`.
Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99
Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
1) If _PRS is present, must have _CRS and _SRS
2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
4) If _SRS is present, probably should have a _DIS (Remark only)
IASL will issue a warning for each missing dependency.
Ignore this warnings for existing ASL code and issue a message when the build is complete.
Change-Id: I28b437194f08232727623009372327fec15215dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since Tiger Lake platform, the HECI1 device can be disabled on
Alder Lake platform using two different mechanism:
A. Using PMC IPC command 0xA9.
B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using
(B) sending sbi message under SMM. A follow up patch to add the
possible options and let platform to choose the applicable one.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1
device can undergo the PCI enumeration and later based on the
mainboard policy the HECI1 device can be disabled.
Mainboards that choose to make HECI1 enable during boot don't override
`DISABLE_HECI1_AT_PRE_BOOT` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I79f2206bee5403c3fb1c999918fbd2177d0d07ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The only option to make HECI1 function disable on Elkhart Lake SoC
platform is using SBI under SMM mode.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
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Enable S3/S0ix wake events for AC connect/disconnect on Alder Lake RVP.
BUG=None
BRANCH=None
TEST=Verify board wakes from S0ix on AC connect/disconnect.
Change-Id: Iaf92821fd69a59624e58cb8af3896e2b6998723f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH:
in RW).
BRANCH=None
BUG=None
TEST=Issue manual recovery and confirm DUT is entering recovery mode.
Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.
This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.
BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Found using:
diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<"
Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move the `configure_pmc_descriptor()` function to SoC scope instead of
having two identical copies in mainboard scope. Add a Kconfig option to
allow mainboards to decide whether to implement this workaround.
Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: I0345aa22b2330d002c3a4bbe5fbadc57d83d73b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I5f2710b2034882a24a041d99e37ec364193d85e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>,
<stdbool.h>, <stdint.h> and <stddef.h> headers.
Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Commit d448f8ce0fe9955e7792f54cc278897152d53590 (drivers/intel/pmc_mux/
conn: Change usb{23}_port_number fields to device pointers) changed the
way the pmc_mux/conn driver gets the corresponding USB ports from the
devicetree. This change didn't include the corresponding change for the
Taniks and Vell variants of the Google Brya project and the Intel
adlrvp_n_ext_ec board which probably weren't in the tree at the time the
patch referenced above was created. This patch ports the needed change
forward to those boards to fix the build of the upstream tree.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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List of changes:
1. Add separate file for ADL-N GPIOs
2. Configure GPIOs as per the schematics of ADL-N RVP
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Run the command below to fix all occurrences.
$ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,'
Change-Id: I84669341e2c8976953284dbaf113da3397857de3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Run the command below to fix all occurrences.
$ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,'
Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.
Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add support for Alder lake N LP5 RVP with board ID 0x7.
Since SPD index 7 is unused earlier, ADL-N will use it.
Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Currently, the pmc_mux/conn driver uses integer fields to store the
USB-2 and USB-3 port numbers from the SoC's point of view. Specifying
these as integers in the devicetree is error-prone, and this
information can instead be represented using pointers to the USB-2 and
USB-3 devices. The port numbers can then be obtained from the paths of
the linked devices, i.e. dev->path.usb.port_id.
Modify the driver to store device pointers instead of integer port
numbers, and update all devicetrees using the driver. These are the
mainboards affected (all are Intel TGL or ADL based):
google/brya
google/volteer
intel/adlrvp
intel/shadowmountain
intel/tglrvp
system76/darp7
system76/galp5
system76/lemp10
Command used to update the devicetrees:
git grep -l "usb._port_number" src/mainboard/ | \
xargs sed -i \
-e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \
-e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g'
BUG=b:208502191
TEST=Build test all affected boards. On brya0, boot device and check
that the ACPI tables generated with and without the change are the same.
Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch removes unused header inclusion as <commonlib/helpers.h>
from several mainboard gpio definition files.
Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae
Signed-off-by: subratabanik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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These boards program the early GPIO table in bootblock, not romstage.
Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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This patch adds the following list of changes:
1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p
devictree.
2. Add support for 2 mainboards as ADL-N board with default EC (Windows
SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from
adlrvp-p.
3. Add mainboard Kconfig to Kconfig.name file
4. Handle mainboard names in Kconfig file for ADLRVP N
5. Add config options to pick the adlrvp_n devicetree
Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The code in these files is meaningless, and can be dropped.
Change-Id: I11571885059e8d5f930f741172c74b25faa09a15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7
SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4
PCH devices are connected on the platform, an external differential
buffer chip needs to be placed at the platform level.
A mainboard designer can choose to add an external clock chip, and
select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER.
CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to
discrete buffer for further distribution to platform.
TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot.
localhost ~ # dmesg | grep mmc
[ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA
[ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB
[ 5.494268] mmcblk0: p1
Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`.
The following mainboards enable the DPTF device in the devicetree
despite `Device4Enable` is not being set.
* google/deltaur
Thus, set it to off to keep the current state unchanged.
Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up `SmbusEnable` FSP setting to devicetree state and drop its
redundant devicetree setting `SmbusEnable`.
The following mainboards enable the SMBus device in the devicetree
despite `SmbusEnable` is not being set.
* google/deltaur
* starlabs/laptop
Thus, set it to off to keep the current state unchanged.
Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207625007
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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ADL-M has its own set of VBT files to pick during execution,
this will avoid any conflict with other ADL variants.
VBT files added at chrome-internal:4138272
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update board type to 4 as per MRC team's input. This
fixes LP5 sagv point 3 being clipped from the expected
5200Mhz to 4800Mhz.
TEST=Boot to OS, verify frequency locked.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The following changes are needed to fix S0ix regression on RVP
1) Disable Clk src 3
2) Disable Ext FIVR settings
TEST=Boot adlrvp to OS, confirm S0ix is working.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016.
This relands commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It's commented in <types.h> that it shall provide <commonlib/helpers.h>.
Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.
Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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MAINBOARD_HAS_CHROMEOS always evaluates true for this board.
The commentary about get_write_protect_state() was wrong, it's
currently only called in ramstage.
Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is
copied to CSE_RW, so the sizes of these regions need to match.
BUG=b:189177538
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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When MMIO functions are available, the pci_s_* functions do exactly
the same thing. Drop the redundant pci_mmio_* versions.
Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status
trusted (LOW: in RO) or untrusted (HIGH: in RW).
Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode on
ADL-M RVP.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS
field, as newer Intel platforms do.
Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This reverts commit 0a1602217fd0d60c59a497cb83a23b44cf4973d9.
EC region is required in order to provide unified coreboot image for
Chrome and Windows SKU RVP's. Also removing EC region causes a regression
for ADL-P platforms.
With this patch EC region is included back into flash map.
Change-Id: I0f7f2b5dd392b08e1978a3b3f3236eac0dab1f12
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
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This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.
BUG=b:189177538
Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig that the configuration
is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: If68c118f22579cc0a3db570119798f0f535f9804
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These changes include ELAN touchpad to ACPI tables and configure GPIO's.
BUG=None
Test=Boot board, touchpad should be functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
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Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic76c29069beb510dd7620f340e0aab212668c3f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig that the configuration
is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
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Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each
variant.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig so that the
configuration is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
|
|
Make the `get_cst_entries()` function provide a read-only pointer. Also,
constify the actual data where applicable.
Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain
to toggle during a switch from DP Alt to TBT Alt modes.
Contrary to DS specifying it may be left unconfigured, hence floating, there are instances
seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp).
Hence configure it to LOW.
Branch=none
Bug=none
Test=Boot to OS, connect TBT dock which enumerates in DP Alt,
Login, TBT dock enumerates in TBT Alt
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Switch to common GNVS. No additional fields to those being present in
common GNVS are used by any SKL/KBL device. Thus, they're dropped
completely.
Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
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The `IRQ_SLOT_COUNT` value is only meaningful when generating a PIRQ
table. None of these boards do it, so specifying this value achieves
absolutely nothing. Drop it to prevent further useless copy-pasting.
Change-Id: I2d63b850c03fc1471c0eef180e8b621311b2c336
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig
does not exist in the coreboot tree (including submodules), drop it.
These files should be stored in the `site-local` subdirectory and the
paths specified for each board in `site-local/Kconfig`. For example:
config VGA_BIOS_FILE
default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200
Note that this is just an example. There are better ways to structure
one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option
would be one of them, though variants may still need special handling.
Also, update autoport to not generate `VGA_BIOS_FILE` defaults.
Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
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This patch enables eNEM flow for ADL-M
TEST=Able to build and boot ADL-M RVP using eNEM mode.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.
TEST=Boot adlrvp to OS, ensure no TPM timeout errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Set PL4 value dynamically for adlrvp board based on CPU SKUs
which is detectable at runtime. These values are based on
platform design specification.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
On 682:
Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000)
Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
These values are as per platform design specification.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This is to fix SSD detectiong failure in warm boot observed
on ADL-M RVP. This patch implements the coreect power sequence:
SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Update to recommended Rcomp drive strength value for DDR4 as per
MRC team's input.
Additionally, add space around the `targets` array.
Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add ADLP 242 sku PLx related settings, which follow the settings of
ADLP 282 sku (both are 15w).
BUG=b:201253904
TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage
Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change replaces the device tree walks with device pointers by
using alias for dptf_policy device.
Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch enables HECI1 interface to allow OS applications to communicate
with CSE.
TEST=Verify PCI device 0:16.0 exposed in the lspci output
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: Ifd338345caa183f03097f1003080992da70296ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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These statements fit on a single line. Reflow them to ease future works.
Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This patch allows ADL-RVP mainboards to set AUX GPIO PADs based
on the board id value.
Various ADL-P and ADL-M RVPs SKUs demand different GPIO AUX programming
hence, this patch implements a helper function inside `adlrvp` mainboard
to override devicetree chip config.
Note: Different ADL-P/M SKUs (LP4/LP5/DDR4/DDR5) don't have dedicated
devicetree for overrides hence, board id is being used for unique SKU
identification.
Additionally, skip AUX GPIO PAD filling up for Windows SKUs.
TEST=Able to override AUX GPIO PADs based on ADL-P RVP board id.
Change-Id: I2f0a37c7a8bd69af715551df2a93e6eed89e954a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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TEST=Boot RVP, ensure Type C ports operate correctly.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Iadc0df2e6e29a5afbcbb7db1ae0be6546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
Kconfig to enable USB4 resources and drops the configuration
in mainboard.
Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add new board variant to enable MCHP1727 Modular EC Card on RVP
BUG=b:179214042
BRANCH=none
TEST=emerge brya and verify that adlrvp_p_mchp images boot
Change-Id: I9dc96ad5c5db21fedbe480d19fcae8434d3bd169
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56839
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP-S hides the PMC from the PCI bus when it runs, but there are still
initialization steps coreboot programs for the PMC. Therefore, change
all of the cannonlake mainboards to set the PMC as hidden in the
devicetree, which means the device will be skipped during enumeration,
but device callbacks are still issued as if the device were enabled.
TEST=Ran full patch train on google/dratini, disassembled SSDT and the
PEPD device matches what is in pep.asl. Also verified via dmesg that the
INT33A1 device is still initialized by the kernel.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I15203920546363466eef567136821b59dda763b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These defines are copy-paste leftovers from Kunimitsu. However, neither
Saddle Brook nor KBLRVP use memory-down, so drop the unneeded defines.
Change-Id: I396aeaa634f619be7be0ee97c0cab1c682f53ff2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The I2C #5 device is already disabled in the devicetree.
Change-Id: Ia4970dc07ef57e8184bce395a446974a22eddb08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Disable devicetree devices disabled in the `SerialIoDevMode` array.
These devices get disabled by FSP-S, and coreboot doesn't see them.
Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig
option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as
coreboot console. However, the LPSS console driver requires the LPSS
UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs).
KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which
makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most
likely results in the UART console not working after FSP-S has run.
This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like
the other KBLRVP variants do.
Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This is most likely a copy-paste remnant, and will never be needed for
RVP8: the SDXC device does not exist on PCH-H (and RVP8 uses a PCH-H).
Change-Id: I69059a88dcdb032beaab5fb03981dccbae0db02e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The I2C #4 and I2C #5 devices do not exist on PCH-H. Disable the devices
using the PCH-H variants' overridetrees (the base devicetree enables I2C
#4), set the `SerialIoDevMode` entries to `PchSerialIoDisabled` and drop
inapplicable I2C #4 voltage settings.
Change-Id: I56f34fa2004993d2123ccd5c1008fd71682ec2bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6346b087543217c78f87751051a4f38b23c566d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The overrides set the options to the same value as drivers/intel/fsp2_0/
Kconfig does, so drop the overrides.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Normally, selecting FSP_USE_REPO will select FSP_FULL_FD which then will
configure the proper paths for FSP_M_FILE and FSP_S_FILE. The override
in these two boards caused FSP_M_FILE and FSP_S_FILE being empty despite
ADD_FSP_BINARIES being selected by FSP_USE_REPO which is an invalid case
that needs to be avoided, so remove the board-level override of those
two options.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I20c8cebea8327d59f0f33d05b824a74bf2121f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The ADD_FSP_BINARIES override in the mainboard's Kconfig caused this
option to not be selected when FSP_USE_REPO is selected. Remove the
override to fix this problem. These two boards are the only ones in tree
that had an override for this option, so now the ADD_FSP_BINARIES option
is only defined in drivers/intel/fsp2_0/Kconfig.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add TPM IRQ config to gpio_m.c, so the TPM IRQ is not allocated
to I2C4.
BUG=NA
BRANCH=None
TEST= boot to os and check cat /proc/interrupts, cr50 SPI interrupt is assigned
and does not conflict with I2C.
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11
0: 36 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 2-edge timer
1: 0 0 0 0 0 0 0 0 9 0 0 0 IO-APIC 1-edge i8042
8: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0
9: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi
14: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC1055:00
16: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 16-fasteoi intel-ipu6
22: 0 13 0 0 0 0 0 0 0 0 0 0 IO-APIC 22-fasteoi idma64.4, i801_smbus, ttyS0
37: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 37-fasteoi idma64.0, i2c_designware.0
38: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 38-fasteoi idma64.1, i2c_designware.1
41: 0 0 0 0 2274 0 0 0 0 0 0 0 IO-APIC 41-edge cr50_spi
42: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 42-fasteoi idma64.2, i2c_designware.2
43: 4 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 43-fasteoi idma64.3, i2c_designware.3
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Id0f3885dec5a6f635254c233709090321491c739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57102
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU
are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M
(internal and external EC SKUs) hence, select those Kconfigs from
mainboard Kconfig rather Kconfig.name.
Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order.
TEST=No changes are seen while the .config file is getting auto
generated.
Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.
Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs.
The BDF for this PCIe slot is pci is: 0000:00:1d.0
TEST = show device command:
$ lspci -s 00:19.0
expect this:
00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change follows other Intel SoCs common way to support SKUs with
bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and
allowing its detection at boottime. It completes support for HCV/DNV
after base SoC patch: commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9
soc/intel/denverton_ns: Ensure CPU device has a valid link
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)."
Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11
Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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