Age | Commit message (Expand) | Author |
---|---|---|
2020-04-02 | soc/intel/tigerlake: Reorganize memory initialization support | Furquan Shaikh |
2020-03-30 | tgl boards: Configure retimer Aux orientation | Brandon Breitenstein |
2020-03-30 | mb/tglrvp: Add GPE configuration | Shaunak Saha |
2020-03-23 | mb/tglrvp: Update Audio AIC settings for Tiger Lake | Srinidhi N Kaushik |
2020-03-18 | mainboard/[g-p]*: Remove copyright notices | Patrick Georgi |
2020-03-16 | mb/intel/tglrvp: Enable ISH driver and register firmware name | li feng |
2020-03-14 | mb/intel/tglrvp: Update GPIO setting | Wonkyu Kim |
2020-03-11 | mb/intel/tglrvp: Enable Hybrid storage mode | Wonkyu Kim |
2020-03-11 | mb/intel/tglrvp: sync up variant folders with latest up3 | Wonkyu Kim |
2020-03-10 | mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation | Srinidhi N Kaushik |
2020-03-09 | mb/intel/tglrvp: Add memory config for Tiger Lake UP4 | Srinidhi N Kaushik |
2020-03-09 | mb/intel/tglrvp: Add TGL UP4 RVP | Wonkyu Kim |