summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/shadowmountain
AgeCommit message (Collapse)Author
2021-09-06mb/intel/shadowmountain: Enable SaGv supportV Sowmya
Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I15203920546363466eef567136821b59dda763b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-19soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik
This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik
This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-23mb/intel/sm: Skip FSP to program UART0Subrata Banik
Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik
Disable all display related UPDs if IGD is not enabled as FSP don't need to perform display port initialization while IGD itself is disabled else assign UPDs based on devicetree config. TEST=Dump FSP-M display related UPDs with IGD enable and disable to ensure patch integrity. Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-05mb/intel/sm: Use device aliasesSubrata Banik
Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all shadowmountain board variants. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-05mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cbSubrata Banik
Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/intel/shadowmountain: Update mainboard propertiesJohn Zhao
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. BUG=b:186521258 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/intel/shadowmountain: Remove power_gpio from baseboardJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-05mb/intel/shadowmountain: Enable early EC Software SyncUsha P
BUG=None TEST=Build and boot to OS on shadowmountain. Ensure that the EC Software Sync is complete. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I8648db685d9c63ed1f2b3e599ca951d6648b7baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/52416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-23mb/intel/shadowmountain: Enable HECI1 interfaceSridhar Siricilla
The patch enables HECI1 interface Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia2638559bcaac78d024e35abd09534b61eacb843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-04-23mb/intel/shadowmountain: Enable RTD3 for SD cardRizwan Qureshi
Enable the PCIe RTD3 driver for the PCIe attached SD card interface and specify the srcclk pin and reset GPIO. TEST=Tested on shadowmountain platform to ensure the system can enter the S0ix state and suspend/resume is stable Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52134 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/alderlake: Add enum for HDA audio configurationSugnan Prabhu S
This change adds an enum to configure the audio related UPDs used for configuring the audio over HDMI/DP and rename a variable for better readability. TEST=On shadowmountain audio sound cards are detected and listed by the Linux kernel. Audio playback and capture is working fine. Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-22soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.hFurquan Shaikh
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure GPIO pads for audio. However, mainboard is expected to perform all GPIO configration in coreboot and hence these UPDs must be set to 0. There is no need to expose these UPDs in chip.h and provide mainboard an option to set these in devicetree. This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from chip.h and the corresponding devicetree in mainboards. Currently, shadowmountain already set these UPDs to 0, whereas adlrvp set these to 1. But all the ADL boards are correctly configuring the GPIO pads for audio, so this change should not impact audio for any of these boards. BUG=b:183482000 TEST=adlrvp and shadowmountain build successfully. Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/alderlake: Drop unused `PrmrrSize` from devicetreeAngel Pons
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the devicetree option's value is not used anywhere, drop it. Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21mb/intel/shadowmountain: Disable GSPI1 interface connected to FPSSridhar Siricilla
The patch disables GSPI1 interface connected to fingerprint scanner since no plans to enable FPS on Shadowmountain. TEST=Verified on Shadowmountain Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic693a8c9699d7d1cceef9ca26305cc34498022d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-10mb/intel/shadowmountain: Enable Bluetooth config in the devicetreeSridhar Siricilla
The patch enables Bluetooth config in the devicetree and removes non-existent Bluetooth PCI interface. TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in the lsusb ouput. Output of lsusb: Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub Bus 003 Device 005: ID 8087:0033 Intel Corp. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/intel/shadowmountain: Add Cr50 supportAamir Bohra
This patch includes changes to add Cr50 support over GSPI0. BUG=b:175579964 TEST=Verify TPM init is done and boots to kernel Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51086 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/shadowwmountain: Enable CSE Lite SKU for shadowmountainSridhar Siricilla
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST=Verified build for Shadowmountain Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-26mb/intel/shadowmountain: Disable the unused CPU PCIe RPV Sowmya
This patch disables the unsued CPU PCIe RP for shadowmountain. TEST= Boot shadowmountain and verify the device is disabled. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17mb/intel/shadowmountain: Update HDMI audio mode to 8TSugnan Prabhu S
This patch sets the HDMI audio mode to 8T as required by the latest FSP version v2081_02 TEST: HDMI audio codecs detection is failing without this change. Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17mb/intel/shadowmountain: Disable xDCISugnan Prabhu S
This patch disables the xDCI which is causing PC8 to PC10 state transitions during sleep. TEST: Confirmed that the transition is happening with this change. Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-15mb/intel/shadowmountain: Add ACPI entry for BT reset GPIOAamir Bohra
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-12mb/intel/shadowmountain: Enable Type-C subsystemV Sowmya
This patch adds the changes to enable the TCSS. BUG=b:175808146 TEST= Boot shadowmountain board, Test the functionality of the Type-C ports on both the mainboard and daughterboard by plugging in the Type-C devices and verified the devices are detected via EC console and in the OS. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27mb/intel/shadowmountain: Add the ASL codeV Sowmya
This reverts commit d510b60f5b4eee6c165039be4acbe89ff25d8a4a. This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27mb/intel/shadowmountain: Add the ramstage codeV Sowmya
This patch includes the ramstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27vboot: update GBB flags to use altfw terminologyJoel Kitching
As per CL:2641346, update GBB flag names: GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW BUG=b:179458327 TEST=make clean && make test-abuild BRANCH=none Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22mb/intel/shadowmountain: Add the romstage codeV Sowmya
This patch includes the romstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early ramstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11Revert "mb/intel/shadowmountain: Add the ASL code"Patrick Georgi
This reverts commit 2151f7561d728a9280d69d20ef56a9fe44db7cb1. Reason for revert: It depends on the shadowmountain ramstage patch. Error on the builder: IASL /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory #include <baseboard/ec.h> ^~~~~~~~~~~~~~~~ compilation terminated. Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11mb/intel/shadowmountain: Add the ASL codeV Sowmya
This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06mb/intel/shadowmountain: Add bootblock and verstage codeV Sowmya
This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-01-28mb/intel/shadowmountain: Add flash layoutV Sowmya
This patch adds the flash layout for shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I7073d9c783684051e33e7a33eca50007d286bb00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-21mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain boardV Sowmya
This patch adds initial support for Alderlake Intel Pre-CEP board called shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 21:21:30 +0000