| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-09-04 | intel/minnowmax: Enable all PCIe ports | Marshall Dawson |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-12-06 | intel/minnowmax: Update devicetree | Martin Roth |
| 2014-12-05 | fsp_baytrail: remove register option for TSEG size | Martin Roth |
| 2014-12-01 | Mark non-executable files non-executable | Patrick Georgi |
| 2014-11-29 | mainboard/intel/minnowmax: use Baytrail Gold3 FSP | York Yang |
| 2014-11-19 | fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.h | Martin Roth |
| 2014-10-29 | minnowmax: Tell the FSP to set TSEG to 8MB | Martin Roth |
| 2014-08-11 | mainboard/intel/minnowmax: Add MinnowMax mainboard | Martin Roth |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |