coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-07-13	mb/intel/kblrvp/variants: Fix indentation and remove empty lines	Felix Singer
2021-03-01	soc/intel/skylake: Clean up SD GPIO handling	Angel Pons
2021-01-21	mb/intel/kblrvp: do UART pad configuration at board-level	Michael Niewöhner
2020-11-13	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	Michael Niewöhner
2020-10-21	soc/intel,mb/*: get rid of legacy pad macros	Michael Niewöhner
2020-09-21	mb/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-08-07	mb/intel/kblrvp: Factor out `HeciEnabled`	Angel Pons
2020-08-04	mb/**/{devicetree,overridetree}.cb: Indent with tabs	Angel Pons
2020-07-29	soc/intel/skylake: Enable SATA depending on devicetree configuration	Felix Singer
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	mainboard/intel: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
2019-12-09	mb/intel/kblrvp: Remove hex values from VR settings	Wim Vervoorn
2019-01-09	mb/intel/kblrvp: Enable overridetree support for variants	Praveen hodagatta pranesh
2018-06-06	soc/intel/common/block: Add common chip config block	Subrata Banik
2018-06-05	soc/intel/skylake: Add option to skip coreboot MP init	Subrata Banik
2017-12-22	soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support	Divya Chellap
2017-10-09	skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI	Furquan Shaikh
2017-08-25	soc/intel/skylake: Add LPC and SPI lock down config option	Subrata Banik
2017-07-24	Fix files with multiple newlines at the end.	Martin Roth
2017-05-01	intel/kblrvp: Enable audio in RVP7 and RVP3	Naresh G Solanki
2017-04-13	soc/intel/skylake: Split AC/DC settings for Deep Sx config	Duncan Laurie
2017-03-15	intel/skylake: Fix bug in VR configuration with FSP 2.0	Duncan Laurie
2016-12-03	mainboard/intel/kblrvp: Enabling Kaby Lake RVP7	Barnali Sarkar