| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-06-06 | soc/intel/common/block: Add common chip config block | Subrata Banik |
| 2018-06-05 | soc/intel/skylake: Add option to skip coreboot MP init | Subrata Banik |
| 2017-12-22 | soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support | Divya Chellap |
| 2017-08-25 | soc/intel/skylake: Add LPC and SPI lock down config option | Subrata Banik |
| 2017-04-13 | soc/intel/skylake: Split AC/DC settings for Deep Sx config | Duncan Laurie |
| 2017-03-15 | intel/skylake: Fix bug in VR configuration with FSP 2.0 | Duncan Laurie |
| 2016-12-03 | mainboard/intel/kblrvp: Enabling Kaby Lake RVP7 | Barnali Sarkar |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |