Age | Commit message (Collapse) | Author |
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UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Ie3878b47b8e20c51b928a38df9ccedf2d50d478e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49431
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"Die()" needs <console/console.h>.
Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update Power Limit2 (PL2) minimum value to the same as maximum value for
jasperlake rvp board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on jasperlake rvp board
Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This change allows treating the PMC as a 'hidden' PCI device on
JasperLake, so that the MMIO & I/O resources can be exposed as
belonging to this device, instead of the system agent and LPC/eSPI.
Original patch for jasperlake SoC here:
CB:42018
This change was missing for JasperLake rvp board.
TEST=Checked PMC init function is called and also checked PCI resource
for PMC device 1f.2.
Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Disable -> Enable
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iccefb02fa9bf9507b9e679b3fba35c5c28d677a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add DTT (Dynamic Tuning Technology) support for Jasper Lake based rvp board.
Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None
BUG=Noe
TEST=Build and boot on jslrvp board
Change-Id: I41409c70d8472c54ca452fc98d5ee9edf3ccd307
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change updates devicetree to enable I2C4 bus required for the UFC
Change-Id: Iade1b64fa3dc890a896fb987fdc8d68db7db5e5f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Jasper Lake SoC had PCI root port mapping swap, thats why we were
using swapped mapping earlier for all the boards
Recently, patch was pushed to handle this swap in PCI enumeration code
for Jasper Lake and we need to correct this mapping. Now this mapping
aligns with actual port mapping in the schematics
BUG=None
BRANCH=None
TEST=NVMe and WLAN are getting detected after this changes
Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This change configures user facing camera related GPIOs
as per schematics.
1. GPP_D5 pwr_en
2. GPP_B14 reset
3. GPP_E0 clock
4. GPP_D12 I2C4b
5. GPP_D13 I2C4b
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: I026c16f73cf597614efaea3e0f0ab1e2cfe1e211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44416
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on JSLRVP.
Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This change updates devicetree to enable SSDT generation for world
facing and user facing cameras of jasperlake_rvp. Also removes DSDT
changes related to the world facing camera.
Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch enables the SkipCpuReplacementCheck config for jasperlake rvp
to avoid the forced MRC training with the soldered down SOC.
BUG=b:160201335
BRANCH=None
TEST=Build and verify on jasperlake rvp with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530
Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Configure GPIOs as per schematics
2. Add 1 Ports and 1 Endpoints
3. Add support for OTVI5675
WFC is on I2C5 with VCM support and using 2 data-lanes
BUG=None
BRANCH=None
TEST=Build and Boot jslrvp board and able to capture image
using world facing camera.
Change-Id: I07ae9e3473c16bde8eb1597460e70cc478357b98
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SataEnable UPD override will be filled using devicetree pci device
status check.
Change-Id: I957dfcf139acd4f4dd5723bc1b010ec45ec91651
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41227
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id49032c0f9b701fe12873c80e1bc0e4b64ba7106
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Used commands:
perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming
Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD
BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.
Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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This CL selects the PcieRpClkReqDetect for the required root ports
which is needed to allow proper clksrc gpio configuration.
Also, sets the unused PcieClkSrcUsage to 0xFF.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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We need to configure GSPI related gpios for external EC and TPM.
Along with GSPI configuring gpios for LAN (power down), FSP_INT
and PCH_INT.
BUG=None
BRANCH=None
TEST=External EC card works and LAN is powered down.
Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable Wifi and Bluetooth for Jasper Lake RVP with following changes:
1. Enable related pci root ports for WLAN and BT
2. Disable unused root ports and clkreq for unused clocks
3. Configure GPIOs properly for M.2 port
BUG=None
BRANCH=None
TEST=Code compiles and able to detect Wifi/BT module on board.
Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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M.2 WWAN interface has GPIOs which requires coreboot to
configure all related GPIOs as per board schematics.
BUG=None
BRANCH=None
TEST=code compiles and WWAN device is detected in OS
Change-Id: I8ad978a619b50e16ad754177f1eb05cf7670b79f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Configure write protect and card detect SD Card GPIO for JSLRVP
as per schematics.
BUG=None
BRANCH=None
TEST=Build, boot JSLRVP and verified SD Card detection.
Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39492
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.
Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable S0ix from devicetree for JSLRVP
TEST= Build, boot JSLRVP and Verified S0ix is
working by running "echo freeze > /sys/power/state"
from kernel console.
Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips
connected on I2C0: DA7219 and MAX98373
1. Enable Kconfig to enable I2C drivers for both chips.
2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry
for I2C0.
3. Enable audio related GPIO configurations.
BUG=None
BRANCH=None
TEST=Checked that dmic and speaker are functional on Jasper Lake RVP
Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop
referring from soc/intel/tigerlake.
Addtionally mainboard changes are done to support build.
BUG=b:150217037
TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: Iad0b394dea017223a5b92fff0cb4c2ed1d5a7bd7
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39402
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add memory initialization parameters for Jasper Lake RVP boards
Jasper Lake RVP supports two variants, one with memory LPDDR4
and another with DDR4
Based on board id, mainboard will pass correct memory parameters
to the fsp.
BUG=None
BRANCH=None
TEST=Check compilation for Jasper Lake RVP and check memory training passes.
Change-Id: Idc92363a2148990df16c2068c7986013d015f604
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39195
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables the SATA config from devicetree for JSL RVP, since we
are not planning to use the SATA storage in chrome config.
Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Configure UPDs to support Audio enablement.
Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Jasper Lake SOC has 8 PCIe root ports. Cleaning up the root ports
as per Jasper Lake. This patch updates the devicetree to enable WLAN
and NVME for jasperlake_rvp and removes the other root port configurations
which are not required.
Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups in coreboot so that they are mapped properly.
GPIO comuinities in coreboot should match with the kernel gpio
communities also. Kernel reads the ASL file from coreboot. This
patch adds the proper community mapping in ASL code to match with
kernel code. In gpio_soc_defs.c file we are indexing the groups
correctly. In gpio.h file we define all the gpio devices as kernel
populates sysfs with separate gpio device for each community. This
patch is created based on Intel Tiger Lake Processor PCH Datasheet
with Document number:575857 and Chapter number:27.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. In /sys/kernel/debug/pinctrl
verify INTC34C5:0<1-3> listing all the pins for each community.
e.g., #cat /sys/kernel/debug/pinctrl/INT34C5:00/pins should list
all the community 0 pins.
Change-Id: I40c386db060d84c1b7fba9c587f960d6a92f84ba
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Update chip files to include :
- Update chip.c based on TGL FSP
- Update chip.h based on TGL FSP
- Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
- Update pmc_utils.c and JSL devicetree for build failure
Reference
PCH EDS#576591 vol1 rev1.2
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tigerlake SoC doesn't have GPIO defined for GPP_G. so compilation is
failing due to this.
We will update correct gpio for sd card detect once we have Jasper Lake
soc gpio patch.
partner bug for tracking: https://ticket.coreboot.org/issues/251
BUG=None
BRANCH=NONE
TEST='jslrvp' mainboard builds successfully
Change-Id: I097b2f3a4fef1a487495a4aa9d2bcf88aa64f017
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.
This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761
Below are the changes done over the copy patch:
1. Rename "Icelake" with "Jasperlake".
2. Replace "icelake_rvp" with "jasperlake_rvp".
3. Rename "icl" with "jsl".
4. Remove unwanted SPD file, add empty SPD as
placeholder.
5. Replace "soc/intel/icelake" with "soc/intel/tigerlake"
as tigerlake SOC hosts jasperlake code as well.
6. Empty romstage_fsp_params.c, to fill it later with
SOC specific config.
7. Empty GPIO configuration, to be filled as per board.
8. Change copyright year to 2019.
9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP
and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
10. Replace icl_u and icl_y variant with jslrvp variant.
11. Remove basebord gpio.c and rely on variant override.
12. Remove HDA verb table and config support.
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs.
2. Clean up devicetree as per jasperlake SOC.
3. Add GPIO support.
4. Update chromeos.fmd to make 10MB BIOS region.
TEST=Build jasperlake rvp board
Change-Id: I3314215807959b7348b71933fbba98e6487c0632
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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