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path: root/src/mainboard/intel/jasperlake_rvp/Kconfig
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2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08mb/intel/jasperlake_rvp: Add DTT support for jslrvpSumeet R Pawnikar
Add DTT (Dynamic Tuning Technology) support for Jasper Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control. BRANCH=None BUG=Noe TEST=Build and boot on jslrvp board Change-Id: I41409c70d8472c54ca452fc98d5ee9edf3ccd307 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-05mb/intel/jasperlake_rvp: Replace static camera ACPI by driverSugnan Prabhu S
This change updates devicetree to enable SSDT generation for world facing and user facing cameras of jasperlake_rvp. Also removes DSDT changes related to the world facing camera. Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-23mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVPKrishna Prasad Bhat
This patch enables CSE Lite SKU for jasperlake rvp. BUG=b:160201335 BRANCH=None TEST=Build and boot jasperlake rvp with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I60039ffb1f24cf98f55e83d8c8649745598aa43a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40571 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPIKyösti Mälkki
Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41703 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-04-28mb/intel/jasperlake_rvp: Configure GPIO for JSLRVPRonak Kanabar
We need to configure GSPI related gpios for external EC and TPM. Along with GSPI configuring gpios for LAN (power down), FSP_INT and PCH_INT. BUG=None BRANCH=None TEST=External EC card works and LAN is powered down. Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/intel/jasperlake_rvp: Update SMBIOS data for JslrvpMeera Ravindranath
1)Change Mainboard Part Number to jslrvp 2)Change Mainboard Family to Intel_jslrvp 3)Generate SMBIOS table and fill sku id information in SMBIOS BUG=None BRANCH=None TEST=Mosys works on jslrvp and Sku ID info is generated Change-Id: Iad0b394fea017223a5b98fff0cb4c2bd1d5a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40011 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13mb/intel/jasperlake_rvp: Enable audioMaulik V Vaghela
Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips connected on I2C0: DA7219 and MAX98373 1. Enable Kconfig to enable I2C drivers for both chips. 2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry for I2C0. 3. Enable audio related GPIO configurations. BUG=None BRANCH=None TEST=Checked that dmic and speaker are functional on Jasper Lake RVP Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26mb/intel/jasperlake_rvp: Correct Kconfig optionsMaulik V Vaghela
1.Select CHROMEOS_EC related Kconfig for variant board with external EC support. 2.Select proper CHROMEOS Kconfigs which are required for all variants. 3.Disable Intel EC region in case of external EC. BUG=None BRANCH=None TEST=Compilation is successful for both Jasper Lake RVP variants. Change-Id: I290b3748777e18476651101de71df9080dd3105c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39584 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02mb/intel/jasperlake_rvp: Add initial mainboard codeAamir Bohra
This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Jasperlake". 2. Replace "icelake_rvp" with "jasperlake_rvp". 3. Rename "icl" with "jsl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake" as tigerlake SOC hosts jasperlake code as well. 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC 10. Replace icl_u and icl_y variant with jslrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per jasperlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 10MB BIOS region. TEST=Build jasperlake rvp board Change-Id: I3314215807959b7348b71933fbba98e6487c0632 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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