coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-05-31	cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE	Nico Huber
2017-06-02	intel/bakersport_fsp: Move into bayleybay_fsp as a variant	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-06	fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO	Alexandru Gagniuc
2015-09-07	intel: Do not hardcode the position of mrc.cache	Alexandru Gagniuc
2015-07-02	Move baytrail & fsp_baytrail to the common IFD interface.	Martin Roth
2015-06-27	Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols	Martin Roth
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-03-05	mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variable	Alexandru Gagniuc
2015-02-24	(bakersport\|bayleybay)_fsp: Do not force a default loglevel	Alexandru Gagniuc
2015-02-24	mainboard: Do not redefine CONSOLE_POST Kconfig variable	Alexandru Gagniuc
2015-02-24	soc/fsp_baytrail: Fix use of microcode-related Kconfig variables	Alexandru Gagniuc
2014-12-06	Remove IRQ_SLOT_COUNT on all boards without PIRQ table.	Vladimir Serbinenko
2014-11-15	fsp: Change mobo partnumbers to reflect that it's running code FSP variant	Vladimir Serbinenko
2014-07-05	intel: Make monotonic timer a first class citizen	Edward O'Callaghan
2014-06-18	intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INIT	Kyösti Mälkki
2014-06-13	fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT	Martin Roth
2014-06-12	bayleybay_fsp Kconfig: Remove unnecessary overrides	Martin Roth
2014-05-30	intel/bayleybay: Add Intel's Bayley Bay mainboard	Martin Roth