coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-11-09	mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp	V Sowmya
2020-11-08	mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'	Subrata Banik
2020-11-07	mb/intel/adlrvp: Configure GPIOs to enable DMIC	Sridhar Siricilla
2020-11-07	mb/intel: Enable ALC711 Audio codec over SNDW0 link	Sridhar Siricilla
2020-11-07	mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers	V Sowmya
2020-11-07	mb/intel/adlrvp: Configure the HPD GPIO's	V Sowmya
2020-11-05	mb/intel/adlrvp: Add support for DDR5 memory	Subrata Banik
2020-11-02	mb, soc/intel: Reorganize CNVi device entries in devicetree	Furquan Shaikh
2020-10-29	mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'	Subrata Banik
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-10-16	mb/intel/adlrvp: Enable Hybrid storage mode	Subrata Banik
2020-10-16	mb/intel/adlrvp: Enable PCIE RP11 for optane	Subrata Banik
2020-10-16	mb/intel/adlrvp: Fix SSD detection issue on ADL RVP	Subrata Banik
2020-10-16	mb/intel/adlrvp: Program GPIO for M.2 PCH SSD	Subrata Banik
2020-10-14	mb/intel/adlrvp: Add ADL-P mainboard ASL code	Subrata Banik
2020-10-14	mb/intel/adlrvp: Add ADL-P ramstage mainboard code	Subrata Banik
2020-10-13	mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devices	Furquan Shaikh
2020-10-13	mb/intel/adlrvp/dsdt.asl: Use macro for DSDT revision	Elyes HAOUAS
2020-10-11	mb/intel/adlrvp: Add ADL-P romstage mainboard code	Subrata Banik
2020-10-08	mb/intel/adlrvp: Add initial ADL-P mainboard code	Subrata Banik