coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-12-01	mb/intel/adlrvp: Add support for LPDDR5	Sridhar Siricilla
	This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-10-11	mb/intel/adlrvp: Add ADL-P romstage mainboard code	Subrata Banik
	List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD TEST=Able to build and boot ADL-P RVP till ramstage early Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>