coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2024-02-22	mb/intel/adlrvp: Remove ADLRVP_M mainboard	Sean Rhodes
2023-07-12	treewide: Drop the suffixes from ADL and RPL CPUID macros and strings	Michał Żygowski
2022-11-04	mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h>	Elyes Haouas
2022-06-07	mb/intel/adlrvp: Add VBT for adlrvp with Raptor Lake silicon	Bora Guvendik
2022-02-25	mb/intel/adlrvp: Add support for MAX98373 codec	Usha P
2022-02-10	mb/intel/adlrvp: Fix vbt loading error	Lean Sheng Tan
2021-12-23	ChromeOS: Refactor ACPI CNVS generation	Kyösti Mälkki
2021-11-22	mb/intel/adlrvp: Use dedicated VBT files for ADL-M	Bernardo Perez Priego
2021-08-10	mb/intel/adlrvp: create dynamic power limits mechanism for thermal	Sumeet Pawnikar
2021-08-09	mb/intel/adlrvp: Support VBT binaries for LP4 and LP5	Bernardo Perez Priego
2021-08-05	mb/intel/adlrvp: Add probed fw_configs to SMBIOS OEM strings	Anil Kumar
2021-06-14	mb/intel/adlrvp: Add board id for MR DDR5 SKU	Deepti Deshatty
2021-04-02	mb/intel/adlrvp: Update VBT filenames	Tim Wawrzynczak
2021-03-15	mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs	Meera Ravindranath
2020-10-14	mb/intel/adlrvp: Add ADL-P ramstage mainboard code	Subrata Banik