coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-01-18	mb/intel/adlrvp: Add wake events for AC connect/disconnect	Krishna Prasad Bhat
2021-12-23	mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP	Krishna Prasad Bhat
2021-11-02	mb/intel/adlrvp: Configure EC in RW GPIO	Anil Kumar
2021-10-01	mb/intel/adlrvp: set PL4 value dynamically for thermal	Sumeet Pawnikar
2021-10-01	mb/intel/adlrvp: set power limits dynamically for thermal	Sumeet Pawnikar
2021-08-10	mb/intel/adlrvp: create dynamic power limits mechanism for thermal	Sumeet Pawnikar
2021-06-14	mb/intel/adlrvp: Add board id for MR DDR5 SKU	Deepti Deshatty
2021-03-28	mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configuration	Maulik V Vaghela
2021-03-28	mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configuration	Maulik V Vaghela
2021-02-22	mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17	Subrata Banik
2020-12-01	mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP	Subrata Banik
2020-12-01	mb/intel/adlrvp: Add support for LPDDR5	Sridhar Siricilla
2020-11-08	mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'	Subrata Banik