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2024-03-19soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by defaultPatrick Rudolph
As of now coreboot only supported one PCI segment group and thus the MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the default FSP doesn't allow to disable unused IIO stacks a patched version had to be used. Those unused IIO stacks consume lots of PCI bus ranges, leaving no free buses for the secondary side behind PCI bridges. The IIO disable mechanism doesn't work after ACPI G3 exit and thus requires multiple reboots when the previous state was G3. Since coreboot now supports multi PCI segment groups enable 512 MMCONF buses on 4S platforms by default and drop the IIO stack disable UPDs on ibm/sbp1. This allows to boot faster without the need for a patched FSP. The use of multiple PCI segment groups might prevent legacy software from working properly, however the only board where multiple PCI segment groups are used uses u-root as default payload. TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups. TEST=intel/archercity CRB Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-06soc/intel/xeon_sp/smihandler: Lock SMM_FEATURE_CONTROL on all socketsPatrick Rudolph
Remove hardcoded B:D:F numbers for the first socket and pass the PCI addresses to be locked within SMM by using the smm_pci_resource_store. This allows to lock down SMM on all sockets without knowing the actual bus topology or PCI segment group at compile time where the UBOX devices reside on. Tested: SMM is locked on all 4 sockets instead of just one. Change-Id: Ica694911384005681662d3d7bed354a60bf08911 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/hp to mb/kontron: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icfdadfa6705a64655b38aca25be0818ec26429f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80110 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-09mb/ibm/sbp1: Set FSP loglevelPatrick Rudolph
Change-Id: Ia97dbda30f657f0b1568364d712eaea8d134b3b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79791 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-13mb/ibm/sbp1: Disable SATA controllerNaresh Solanki
SATA controller isn't used & hence disable. Change-Id: Iab2d597e6a0f22b946e657a2851b68f752d1f7d4 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77893 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/ibm/sbp1: call soc soc_config_iio to configure IIO UPDJohnny Lin
Change-Id: I56ee0d4a26931fe05d2d35046325901930086e35 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76344 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-03mb/ibm/sbp1/Kconfig: Remove unused MAX_SOCKET_UPDElyes Haouas
Change-Id: I5d9133f2255a96c8367f69dcbb198a1a142cdb82 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-25mb/ibm/sbp1: Improve SMBIOS type 17 entriesPatrick Rudolph
Add bank locator and slot existance to the mainboard code. TEST: Verified on Linux that all slots show in dmidecode -t 17. Change-Id: I4ced36e26368d3f99a7341cb55a8deb118b2d1a4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-25mb/ibm/sbp1: Drop SuperIO codePatrick Rudolph
The SuperIO is not used so don't enable decoding of 0xE2 and drop all code using it. It's not even required for the virtual UART on 0x3f8 to work. Add the virtual UART on 0x3f8 as ACPI device. TEST: Verified on SBP1 that serial still works. Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-12mb/ibm/sbp1: Disable SIO UartsNaresh Solanki
Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead. TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC console. Also made sure coreboot logs are accessible via VUART. Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-12mb/ibm/sbp1: Set coreboot ready GPIO in BS_PAYLOAD_BOOTNaresh Solanki
Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS completion. Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28mb/ibm: Add 4 SPR sockets server board IBM SBP1Patrick Rudolph
The IBM SBP1 is an evaluation platform. It's utilising: - 4 SPR sockets, having 16 DIMMs each - 240C/480T at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM It has an AST2600 BMC for remote management. It doesn't have: - External facing USB ports - Video outputs - Audio codec Test: The board boots to Linux 5.15 with all 480 cores available. All PCIe devices are working and no errors in ACPI. All 64 memory DIMMS are working and M.2 devices can be used. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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