mb/ibm: Add 4 SPR sockets server board IBM SBP1

The IBM SBP1 is an evaluation platform.

It's utilising:
- 4 SPR sockets, having 16 DIMMs each
- 240C/480T at maximum
- 32x CPU PCIe slots
- 2x M.2 PCH PCIe slots
- Dual 200Gbit/s NIC
- SPI TPM

It has an AST2600 BMC for remote management.

It doesn't have:
- External facing USB ports
- Video outputs
- Audio codec

Test:
  The board boots to Linux 5.15 with all 480 cores available.
  All PCIe devices are working and no errors in ACPI.
  All 64 memory DIMMS are working and M.2 devices can be used.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

12 files changed, 800 insertions, 0 deletions

diff --git a/src/mainboard/ibm/sbp1/Kconfig b/src/mainboard/ibm/sbp1/Kconfig
new file mode 100644
index 0000000000..69974862e5
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/Kconfig
@@ -0,0 +1,39 @@
+if BOARD_IBM_SBP1
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select IPMI_KCS
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_USES_FSP2_0
+	select SOC_INTEL_SAPPHIRERAPIDS_SP
+	select SUPERIO_ASPEED_AST2400 # Check if AST2400 is compatible
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_USES_IFD_GBE_REGION
+
+config MAINBOARD_DIR
+	string
+	default "ibm/sbp1"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "SBP1"
+
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config MAX_SOCKET
+	int
+	default 4
+
+config MAX_SOCKET_UPD
+	int
+	default 4
+
+config MAX_CPUS
+	int
+	default 480
+
+endif
diff --git a/src/mainboard/ibm/sbp1/Kconfig.name b/src/mainboard/ibm/sbp1/Kconfig.name
new file mode 100644
index 0000000000..fec27e6bf5
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_IBM_SBP1
+	bool "SBP1"
diff --git a/src/mainboard/ibm/sbp1/Makefile.inc b/src/mainboard/ibm/sbp1/Makefile.inc
new file mode 100644
index 0000000000..0688aa1973
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+ramstage-y += ramstage.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/ibm/sbp1/acpi/platform.asl b/src/mainboard/ibm/sbp1/acpi/platform.asl
new file mode 100644
index 0000000000..7ab8f8e27b
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/acpi/platform.asl
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+Name (_S0, Package () // mandatory system state
+{
+	0x00, 0x00, 0x00, 0x00
+})
+
+Name (_S5, Package ()  // mandatory system state
+{
+	0x07, 0x00, 0x00, 0x00
+})
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/ibm/sbp1/board.fmd b/src/mainboard/ibm/sbp1/board.fmd
new file mode 100644
index 0000000000..708d4b21c0
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/board.fmd
@@ -0,0 +1,11 @@
+FLASH@0xfc000000 64M {
+	SI_ALL@0x0 0x03000000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x2fff000
+	}
+	RW_MRC_CACHE@0x3000000 0x10000
+	FMAP 0x800
+	RW_VPD(PRESERVE) 0x4000
+	RO_VPD(PRESERVE) 0x4000
+	COREBOOT(CBFS)
+}
diff --git a/src/mainboard/ibm/sbp1/board_info.txt b/src/mainboard/ibm/sbp1/board_info.txt
new file mode 100644
index 0000000000..851095425f
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: IBM
+Board name: SBP1
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/ibm/sbp1/bootblock.c b/src/mainboard/ibm/sbp1/bootblock.c
new file mode 100644
index 0000000000..9aca04e1ef
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/bootblock.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+#define PCR_DMI_LPCIOD  0x2770
+#define PCR_DMI_LPCIOE  0x2774
+
+void bootblock_mainboard_early_init(void)
+{
+	uint16_t lpciod = LPC_IOD_COMA_RANGE;
+	uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8) and superio (0x2e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+
+	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb
new file mode 100644
index 0000000000..098fd9a8eb
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/devicetree.cb
@@ -0,0 +1,36 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/spr
+
+	device domain 0 on
+		device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3
+
+		device pci 1f.0 on         # Intel device 1b81: PCH eSPI controller
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on      # SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on      # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+					end
+				end
+			end
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+			end
+			chip drivers/pc80/tpm # TPM
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.3 off end # Intel device 1bc8: PCH audio
+		device pci 1f.6 off end # Intel device 1bcb: PCH GbE controller
+	end
+end
diff --git a/src/mainboard/ibm/sbp1/dsdt.asl b/src/mainboard/ibm/sbp1/dsdt.asl
new file mode 100644
index 0000000000..272fca2836
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/dsdt.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	// platform ACPI tables
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	// SPR-SP ACPI tables
+	#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
+
+	// LPC related entries
+	Scope (\_SB.PC00)
+	{
+		#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h b/src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h
new file mode 100644
index 0000000000..61a2437dc0
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+	/* ------- GPIO Group GPPC_A ------- */
+	/* PCH default for ESPI inter GPPC_A0-A9 */
+	/* Unused */
+	PAD_NC(GPPC_A10, NONE),
+	PAD_NC(GPPC_A11, NONE),
+	PAD_NC(GPPC_A12, NONE),
+	PAD_NC(GPPC_A13, NONE),
+	PAD_NC(GPPC_A14, NONE),
+	PAD_NC(GPPC_A15, NONE),
+	PAD_NC(GPPC_A16, NONE),
+	PAD_NC(GPPC_A17, NONE),
+	PAD_NC(GPPC_A18, NONE),
+	PAD_NC(GPPC_A19, NONE),
+
+	/* ------- GPIO Group GPPC_B ------- */
+	/* PTI */
+	PAD_CFG_NF(GPPC_B0, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B1, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B2, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B3, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B4, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B5, NONE, DEEP, NF4),
+	/* GPPC_B12-B23 - PTI */
+	PAD_CFG_NF(GPPC_B12, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B13, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B14, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B15, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B16, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B17, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B18, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B19, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B20, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B21, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B22, NONE, DEEP, NF4),
+	PAD_CFG_NF(GPPC_B23, NONE, DEEP, NF4),
+	/* USB2_OC1_N */
+	PAD_NC(GPPC_B6, NONE),
+	/* USB2_OC2_N */
+	PAD_NC(GPPC_B7, NONE),
+	/* USB2_OC3_N */
+	PAD_NC(GPPC_B8, NONE),
+	/* USB2_OC4_N */
+	PAD_NC(GPPC_B9, NONE),
+	/* USB2_OC5_N */
+	PAD_NC(GPPC_B10, NONE),
+	/* USB2_OC6_N */
+	PAD_NC(GPPC_B11, NONE),
+
+	/* ------- GPIO Community 1 ------- */
+	/* ------- GPIO Group GPPC_C ------- */
+	/* ME_SML0CLK */
+	PAD_CFG_NF(GPPC_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPPC_C1, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPPC_C2, NONE, DEEP, NF1),
+
+	/* FM_BIOS_POST_CMPLT_N */
+	PAD_CFG_GPO(GPPC_C17, 1, DEEP),
+
+	/* No Connect */
+	PAD_NC(GPPC_C3, NONE),
+	PAD_NC(GPPC_C4, NONE),
+	PAD_NC(GPPC_C5, NONE),
+	PAD_NC(GPPC_C6, NONE),
+	PAD_NC(GPPC_C7, NONE),
+	PAD_NC(GPPC_C8, NONE),
+	PAD_NC(GPPC_C9, NONE),
+	PAD_NC(GPPC_C10, NONE),
+	PAD_NC(GPPC_C11, NONE),
+	PAD_NC(GPPC_C12, NONE),
+	PAD_NC(GPPC_C13, NONE),
+	PAD_NC(GPPC_C14, NONE),
+	PAD_NC(GPPC_C15, NONE),
+	PAD_NC(GPPC_C16, NONE),
+	PAD_NC(GPPC_C18, NONE),
+	PAD_NC(GPPC_C19, NONE),
+	PAD_NC(GPPC_C20, NONE),
+	PAD_NC(GPPC_C21, NONE),
+
+	/* ------- GPIO Group GPPC_S ------- */
+	PAD_NC(GPPC_S0, NONE),
+	PAD_NC(GPPC_S1, NONE),
+	PAD_NC(GPPC_S2, NONE),
+	PAD_NC(GPPC_S3, NONE),
+	PAD_NC(GPPC_S4, NONE),
+	PAD_NC(GPPC_S5, NONE),
+	PAD_NC(GPPC_S6, NONE),
+	PAD_NC(GPPC_S7, NONE),
+	PAD_NC(GPPC_S8, NONE),
+	PAD_NC(GPPC_S10, NONE),
+	PAD_NC(GPPC_S11, NONE),
+
+	/* FM_SMI_ACTIVE_N */
+	PAD_CFG_NF(GPPC_S9, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_D ------- */
+	/* SMB_HOST_STBY_BMC_LVC3_R2 */
+	PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+	/* PLTRST PCHHOT_N */
+	//PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+	//PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+
+	/* No Connect */
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Community 2 ------- */
+	/* ------- GPIO Group GPP_O ------- */
+	/* Unused */
+	PAD_NC(GPP_O0, NONE),
+	PAD_NC(GPP_O7, NONE),
+
+	/* ------- GPIO Community 3 ------- */
+	/* ------- GPIO Group GPP_E ------- */
+	/* Unused */
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E6, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E14, NONE),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+
+	/* SS2/SS1 SATA/PCIE gpio */
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+	/* SSD2/SSD1 DEVSLP */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF2),
+
+	PAD_CFG_GPI(GPP_E15, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+
+	/* ------- GPIO Community 4 ------- */
+	/* -------- GPIO Group GPPC_H -------- */
+	/* Unused */
+	PAD_NC(GPPC_H0, NONE),
+	PAD_NC(GPPC_H1, NONE),
+	PAD_NC(GPPC_H6, NONE),
+	PAD_NC(GPPC_H7, NONE),
+	PAD_NC(GPPC_H15, NONE),
+	PAD_NC(GPPC_H16, NONE),
+	PAD_NC(GPPC_H17, NONE),
+	PAD_NC(GPPC_H18, NONE),
+	PAD_NC(GPPC_H19, NONE),
+
+	/* ------- GPIO Group GPP_J ------- */
+	/* Use PCH defaults */
+	/* GPP_J0 CPUPWRGD */
+	/* GPP_J1 CPU_THRMTRIP_N */
+	/* GPP_J2 PLTRST_CPU_N */
+	/* GPP_J3 TRIGGER0_N */
+	/* GPP_J4 TRIGGER1_N */
+	/* GPP_J5 CPU_PWER_DEBUG_N */
+	/* GPP_J6 CPU_MEMTRIP_N */
+	/* GPP_J7 CPU_MSMI_N */
+	/* GPP_J12 CPU_ERR0_N */
+	/* GPP_J13 CPU_CATERR_N */
+	/* GPP_J14 CPU_ERR1_N */
+	/* GPP_J15 CPU_ERR2_N */
+
+	/* ------- GPIO Community 5 ------- */
+	/* ------- GPIO Group GPP_I ------- */
+	/* Unused */
+	PAD_NC(GPP_I12, NONE),
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+	PAD_NC(GPP_I15, NONE),
+	PAD_NC(GPP_I16, NONE),
+	PAD_NC(GPP_I17, NONE),
+	PAD_NC(GPP_I22, NONE),
+	PAD_NC(GPP_I23, NONE),
+	/* SPI TPM IRQ */
+	PAD_CFG_GPI(GPP_I17, NONE, DEEP),
+
+	/* ------- GPIO Group GPP_L ------- */
+	/* Chip default */
+	/* GPP_L_0 PM_SYNC_0 */
+	/* GPP_L_1 PM_DOWN_0 */
+
+	/* Unused */
+	PAD_NC(GPP_L3, NONE),
+	PAD_NC(GPP_L4, NONE),
+	/* FM_PASSWORD_CLEAR_N */
+	PAD_NC(GPP_L5, NONE),
+	PAD_NC(GPP_L6, NONE),
+	PAD_NC(GPP_L7, NONE),
+	PAD_NC(GPP_L8, NONE),
+
+	/* ------- GPIO Group GPP_M ------- */
+	/* Unused */
+	PAD_NC(GPP_M0, NONE),
+	PAD_NC(GPP_M1, NONE),
+	PAD_NC(GPP_M2, NONE),
+	PAD_NC(GPP_M3, NONE),
+	PAD_NC(GPP_M4, NONE),
+	PAD_NC(GPP_M5, NONE),
+	PAD_NC(GPP_M6, NONE),
+	PAD_NC(GPP_M7, NONE),
+	PAD_NC(GPP_M8, NONE),
+	PAD_NC(GPP_M11, NONE),
+	PAD_NC(GPP_M12, NONE),
+	PAD_NC(GPP_M15, NONE),
+	PAD_NC(GPP_M16, NONE),
+	PAD_NC(GPP_M17, NONE),
+
+	/* ------- GPIO Group GPP_N ------- */
+	/* Unused */
+	PAD_NC(GPP_N1, NONE),
+	PAD_NC(GPP_N4, NONE),
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/ibm/sbp1/ramstage.c b/src/mainboard/ibm/sbp1/ramstage.c
new file mode 100644
index 0000000000..11d0a8b6d3
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+#include "include/spr_sbp1_gpio.h"
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	/* configure Emmitsburg PCH GPIO controller after FSP-M */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c
new file mode 100644
index 0000000000..afb1cf5a19
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/romstage.c
@@ -0,0 +1,349 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/romstage.h>
+#include <defs_cxl.h>
+#include <hob_iiouds.h>
+
+
+/* For now only set 3 fields and hard-coded others, should be extended in the future */
+#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp)	\
+	{						\
+		.SLOTEIP = 0,				\
+		.SLOTHPCAP = slotimp,			\
+		.SLOTHPSUP = slotimp,			\
+		.SLOTPIP = 0,				\
+		.SLOTAIP = 0,				\
+		.SLOTMRLSP = 0,				\
+		.SLOTPCP = 0,				\
+		.SLOTABP = 0,				\
+		.SLOTIMP = slotimp,			\
+		.SLOTSPLS = 0,				\
+		.SLOTSPLV = slotimp ? 25 : 0,		\
+		.SLOTPSP = slotpsp,			\
+		.VppEnabled = 0,			\
+		.VppPort = 0,				\
+		.VppAddress = 0,			\
+		.MuxAddress = 0,			\
+		.ChannelID = 0,				\
+		.PciePortEnable = !pexphide,		\
+		.PEXPHIDE = pexphide,			\
+		.HidePEXPMenu = pexphide,		\
+		.PciePortOwnership = 0,			\
+		.RetimerConnectCount = 0,		\
+		.PcieMaxPayload = 0x7,			\
+		.PcieHotPlugOnPort = slotimp,		\
+	}
+
+#define IIO_PORT_SETTINGS (1 + 5 * 8)
+
+static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY
+sbp1_socket_config[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = {
+	{
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(0, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 Not Used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 12), /* 26:01.0 RSSD12 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 11), /* 26:03.0 RSSD11 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 10), /* 26:05.0 RSSD10 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 9),  /* 26:07.0 RSSD09 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 13), /* 37:01.0 RSSD13 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 14), /* 37:03.0 RSSD14 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 15), /* 37:05.0 RSSD15 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 16), /* 37:07.0 RSSD16 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:01.0 - NIC2*/
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:05.0 - NIC1 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 Not Used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	},
+	{
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 Not Used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 28), /* 26:01.0 RSSD28 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 27), /* 26:03.0 RSSD27 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 26), /* 26:05.0 RSSD26 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 25), /* 26:07.0 RSSD25 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 29), /* 37:01.0 RSSD29 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 30), /* 37:03.0 RSSD30 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 31), /* 37:05.0 RSSD31 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 32), /* 37:07.0 RSSD32 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 Not used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:01.0 - NIC2 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:05.0 - NIC1 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	},
+	{
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 Not Used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 Not used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 17), /* 48:01.0 - RSSD17 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 18), /* 48:03.0 - RSSD18 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 19), /* 48:05.0 - RSSD19 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 20), /* 48:07.0 - RSSD20 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 24), /* 59:01.0 - RSSD24 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 23), /* 59:03.0 - RSSD23*/
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 22), /* 59:05.0 - RSSD22 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 21), /* 59:07.0 - RSSD21 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	},
+	{
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 Not Used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 Not used */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 1), /* 48:01.0 - RSSD01 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 2), /* 48:03.0 - RSSD02 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 3), /* 48:05.0 - RSSD03 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 4), /* 48:07.0 - RSSD04 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */
+	CFG_UPD_PCIE_PORT(0, 1, 8), /* 59:01.0 - RSSD08 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 7), /* 59:03.0 - RSSD07*/
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 6), /* 59:05.0 - RSSD06 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 5), /* 59:07.0 - RSSD05 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	},
+};
+
+static const UINT8 sbp1_socket_config_iou[CONFIG_MAX_SOCKET][5] = {
+	{
+		IIO_BIFURCATE_xxxxxxxx,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_xxxxxxxx,
+	},
+	{
+		IIO_BIFURCATE_xxxxxxxx,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_xxxxxxxx,
+		IIO_BIFURCATE_x4x4x4x4,
+	},
+	{
+		IIO_BIFURCATE_xxxxxxxx,
+		IIO_BIFURCATE_xxxxxxxx,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_x4x4x4x4,
+	},
+	{
+		IIO_BIFURCATE_xxxxxxxx,
+		IIO_BIFURCATE_xxxxxxxx,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_x4x4x4x4,
+		IIO_BIFURCATE_x4x4x4x4,
+	},
+};
+
+static void mainboard_config_iio(FSPM_UPD *mupd)
+{
+	UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig;
+	int port, socket;
+
+	PciePortConfig = (UPD_IIO_PCIE_PORT_CONFIG *)(UINTN)mupd->FspmConfig.IioPcieConfigTablePtr;
+	assert(mupd->FspmConfig.IioPcieConfigTableNumber == CONFIG_MAX_SOCKET);
+
+	for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) {
+
+		/* Array sbp1_socket_config only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
+		for (port = 0; port < IIO_PORT_SETTINGS; port++) {
+			const UPD_IIO_PCIE_PORT_CONFIG_ENTRY *port_cfg = &sbp1_socket_config[socket][port];
+			PciePortConfig[socket].SLOTIMP[port] = port_cfg->SLOTIMP;
+			PciePortConfig[socket].SLOTPSP[port] = port_cfg->SLOTPSP;
+			PciePortConfig[socket].SLOTHPCAP[port] = port_cfg->SLOTHPCAP;
+			PciePortConfig[socket].SLOTHPSUP[port] = port_cfg->SLOTHPSUP;
+			PciePortConfig[socket].SLOTSPLS[port] = port_cfg->SLOTSPLS;
+			PciePortConfig[socket].SLOTSPLV[port] = port_cfg->SLOTSPLV;
+			PciePortConfig[socket].VppAddress[port] = port_cfg->VppAddress;
+			PciePortConfig[socket].SLOTPIP[port] = port_cfg->SLOTPIP;
+			PciePortConfig[socket].SLOTAIP[port] = port_cfg->SLOTAIP;
+			PciePortConfig[socket].SLOTMRLSP[port] = port_cfg->SLOTMRLSP;
+			PciePortConfig[socket].SLOTPCP[port] = port_cfg->SLOTPCP;
+			PciePortConfig[socket].SLOTABP[port] = port_cfg->SLOTABP;
+			PciePortConfig[socket].VppEnabled[port] = port_cfg->VppEnabled;
+			PciePortConfig[socket].VppPort[port] = port_cfg->VppPort;
+			PciePortConfig[socket].MuxAddress[port] = port_cfg->MuxAddress;
+			PciePortConfig[socket].PciePortEnable[port] = port_cfg->PciePortEnable;
+			PciePortConfig[socket].PEXPHIDE[port] = port_cfg->PEXPHIDE;
+			PciePortConfig[socket].PcieHotPlugOnPort[port] = port_cfg->PcieHotPlugOnPort;
+			PciePortConfig[socket].PcieMaxPayload[port] = port_cfg->PcieMaxPayload;
+		}
+		/* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
+		for (port = IIO_PORT_SETTINGS; port < MAX_IIO_PORTS_PER_SOCKET; port++) {
+			PciePortConfig[socket].PEXPHIDE[port] = 1;
+			PciePortConfig[socket].HidePEXPMenu[port] = 1;
+			PciePortConfig[socket].PciePortEnable[port] = 0;
+		}
+		for (port = 0; port < 5; port++)
+			PciePortConfig[socket].ConfigIOU[port] = sbp1_socket_config_iou[socket][port];
+	}
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	UINT32 *sktbmp;
+
+	/* Set Rank Margin Tool to disable. */
+	mupd->FspmConfig.EnableRMT = 0x0;
+
+	/* Set Promote Warnings to disable. */
+	/* Determines if warnings are promoted to system level. */
+	mupd->FspmConfig.promoteWarnings = 0x0;
+
+	/* Set FSP debug message to Disable */
+	mupd->FspmConfig.serialDebugMsgLvl = 0x0;
+
+	/* Force 256MiB MMCONF (Segment0) only */
+	mupd->FspmConfig.mmCfgSize = 0x2;
+	mupd->FspmConfig.PcieHotPlugEnable = 1;
+
+	/*
+	 * Disable unused IIO stack:
+	 * Socket 0 : IIO1, IIO4
+	 * Socket 1 : IIO1, IIO2
+	 * Socket 2 : IIO1, IIO5
+	 * Socket 3 : IIO1, IIO5
+	 * Stack Disable bit mapping is:
+	 * IIO stack number:  1 2 3 4 5
+	 * Stack Disable Bit: 1 5 3 2 4
+	 */
+	sktbmp = (UINT32 *)&mupd->FspmConfig.StackDisableBitMap[0];
+	sktbmp[0] = BIT(1) | BIT(2);
+	sktbmp[1] = BIT(1) | BIT(5);
+	sktbmp[2] = BIT(1) | BIT(4);
+	sktbmp[3] = BIT(1) | BIT(4);
+	mainboard_config_iio(mupd);
+}