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2021-07-02mb/google/dedede/var/magolor: Enable G2 touchscreen for magmaTyler Wang
Add G2 touchscreen support for magma. BUG=b:189852808 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3e032bff7f3e97f54f3e544035e862058ea0dbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2021-07-02mb/google/volteer/variants/eldrid: Include SPD for MT40A512M16TB-062E:RMark Hsieh
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R. Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated with MT40A512M16TB-062E:R DDR4 memory parts. BUG=b:192380070 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01mb/google/hatch/scout: update gpios and device treeJeff Chase
Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart BUG=b:187078663 TEST=boot scout BRANCH=none Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/google/brya: Swap P-sensor IRQEric Lai
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct P-sensor. BUG=b:192331122,b:181555900 TEST=check P-sensor driver can be probed without error. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/google/dedede: Create cappy2 variantSunway
Create the cappy2 variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192035460 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY2 Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/brya/variants/primus: Update mainboard properties for BB retimer ↵Casper Chang
upgrade This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:55348 BUG=b:191897776 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-01mb/google/dedede/var/drawcia: Add LTE modem support for drawperKevin Chiu
Add LTE modem to devicetree. Configure GPIO control for LTE modem by fw_config. Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:186393848 TEST=Build image and check with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/dedede/var/kracko: Update LTE USB port configurationTony Huang
Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:178092096 BRANCH=dedede TEST=Build and boot to OS to check LTE by modem status Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30mb/google/brya/variants/gimble: init overridetree for gimbleMark Hsieh
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf BUG=b:191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3f6875ef438b147436605629445d346a56896a87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30mb/google/brya/variants/primus: update gpiosCasper Chang
set GPP_C3 and GPP_C4 as NC since LAN function removal. BUG=b:190643562 Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30ec/google: Use EC_HOST_EVENT_NONERob Barnes
google_chromeec_get_event returns 0 for no event. Return EC_HOST_EVENT_NONE=0 to improve readability. BUG=b:184074997 TEST=Build and boot guybrush without error Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0Tao Xia
This change adds fine-tuned USB2 PHY parameters for storo. BUG=191089827 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30mb/google/dedede/var/storo: Enable Wifi SAR for storoTao Xia
BUG=b:190027970,b:178175837 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I7084f9b7be2b66adda2d9d5a83ce5dd9c31d01b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30mb/google/brya: Set GPP_B3 to APIC modeEric Lai
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict. BUG=b:181555900 TEST=check dmesg there are no IRQ request errors like below. genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1) Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-29mb/google/guybrush: Initialize WWAN for USB if requestedMartin Roth
To set the Fibocom 850-GL module to USB mode, it needs to be disabled when PCIe training happens, or it will automatically switch to PCIe mode. This patch makes sure it's shut down when training happens in FSP-M. It will be brought up in ramstage and will be available for USB enumeration later. BUG=b:187316460 TEST=Run lsusb from the OS and see that the Fibocom module is present on USB. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/guybrush: Update romstage power-on timings for PCIeMartin Roth
This configures the romstage portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe devices out of reset, both need to be brought hign. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/guybrush: Update bootblock power-on timings for PCIeMartin Roth
This configures the bootblock portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. Setting the PCIE Reset happens in coreboot instead of in the FSP. The Aux reset lines are anded with the PCIe RST line, so both have to be brought up together. On v1 of guybrush, the PCIe reset line also resets EC communication, so it must be brought up immediately on that version. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/herobrine: Add Senor and Piglin variantsShelley Chen
Add configs for Herobrine variants. Also enable ec sw sync as this should not be disabled by default. BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-29mb/google/guybrush: provide full range backlight settings to kernelPratik Vishwakarma
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:190443612 Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835 Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/brya0: Enable MIPI UFCVarshit B Pandya
1. Add 2 port 2 endpoint 2. Add support for OVTI5675 3. Guard entries in override device tree by FW_CONFIG MIPI UFC is on I2C2 This configuration is as per P2 schematics BUG=b:190674542 TEST=Build and Boot on Brya Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/guybrush: Configure eSPI requirements before setting it upMartin Roth
When initializing eSPI early, guybrush has requirements to configure the bus properly. Those are normally run in bootblock_mainboard_early_init, but when setting up eSPI early, those have not run yet. BUG=192100564 TEST=Build along with previous patch, eSPI works on guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/volteer/var/volet: add G2 touch supportSheng-Liang Pan
Enable G2 touchscreen support for Volet. BUG=b:185097280 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I907356448b5d5cbf3974717654ea09cd995962f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55835 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/blipper: Update devicetree and gpio settingZanxi Chen
To reduce power load, set unused GPIOs to NC and close unused interface in devicetree. GPIOs and interfaces are as below: GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07 Interface: I2C1/I2C3/I2C5 USB: port2_3/2_4/2_6 BUG=b:185044041 BRANCH=dedede TEST=Built bios and test, it reduces power load without affecting device function. Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com>
2021-06-28mb/google/brya0: Add FW_CONFIG for UFCVarshit B Pandya
UFC on brya can be USB or MIPI Add FW_CONFIG bit for this option Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-28mb/google/brya: Update mainboard properties for BB retimer upgradeMaulik V Vaghela
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:54292 BUG=b:186521258 TEST=Updated BB retimer FW from 3.4 to 3.5 without any device connected. Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/dedede/var/sasukette: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-28mb/google/dedede/var/cret: Add ssfc codec cs42l42 supportDtrain Hsu
Add cs42l42 codec support in cret. BUG=b:188623237, b:189073353 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/pirika: Update DPTF parametersAlex1 Kao
Update DPTF parameters from internal thermal team. BUG=b:190518303 BRANCH=None TEST=emerge-dedede coreboot Change-Id: I4005047e0c5f39a12c161a92fbd0afaaec1dc976 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/pirika: Support audio AMP auto modeAlex1 Kao
Support audio AMP selection with fw_config. BUG=b:188446060 BRANCH=None. TEST=built pass Change-Id: Idf0eb2a87bfa9665e61d185e37adb90987f3cefb Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/blipper: Enable ELAN touchscreenZanxi Chen
Modify driver from hid to generic(ELAN0001 that used generic driver without hid). BUG=b:191620724 BRANCH=dedede TEST=build bios and boot, touchscreen will work properly. Change-Id: Ife77d514d9906049f237edd169bc07bb53c48579 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
2021-06-26mb/google/brya/variants/primus: init overridetree for PrimusCasper Chang
init overridetree.cb based on the schematic ver MB_20210616C. BUG=b:191897776, b:191897775 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I185b36e34d24b703092e3798e91c70ce3912b11f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-25mb/google/{octopus,reef}: Fix size of SI_BIOS region in default.fmdMatt DeVillier
0xf7f000 - 0x1000 = 0xf7e000, not 0xf6f000. This fixes build failure when selecting the option to validate the layout using the flash descriptor (CONFIG_VALIDATE_INTEL_DESCRIPTOR) Test: build google/casta successfully with IFD validation selected Change-Id: I6df67f76f5d766a9f4f85ffc3e1f0de4a241f509 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55815 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the only memory parts used by primus for Proto build and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:186091208,b:189169995 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I423fd9ad4349c51c6e6b166734ae706509d6ac3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25mb/google/volteer/var/chronicler: add chronicler memory configuration and ↵Sheng-Liang Pan
gpio and devicetree settings add memory configuration for chronicler, based on schematic and gpio table, update gpio and devicetree settings for chronicler. BUG=b:187318819 BRANCH=None TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage verify bootable with chronicler Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Id5524b97a236dcc64d18ab1cd2ce13f6bb2d998f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55340 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/octopus: add audio codec into SSFC support for Garg/GarfourKevin Chiu
BUG=b:191213716 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/guybrush: Change ACPI HID for machine driverYu-Hsuan Hsu
To avoid from using same the name AMDI5682 as Zork, changing to use AMDI1019. The corresponding kernel change is on CL:2929864 BUG=b:189297564 TEST=Audio works with the corresponding kernel change. Cq-Depend: chromium:2929864 Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Change-Id: Ie89302f3b6cd3edb8253b909fde4722c2ea1e102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55508 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/brya: add generic LPDDR4 SPDs for GimbleMark Hsieh
Add Makefile.inc to include three generic LPDDR4 SPDs for the following parts for Gimble: DRAM Part Name DRAM ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) H9HCNNNCPMMLXR-NEE 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I60f95ac5ed7f3134882f6580335ec33632676796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25mb/google/brya/variants/gimble: set up gpioMark Hsieh
Set the GPIO configuration of gimble BUG=b:191213263 Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I667943578a2bf58cc5841564b8df5b6469d7594b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55717 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24mb/google/trogdor: Add new vaviant mrblandZanxi Chen
New boards introduced to trogdor family. BUG=b:191800434 BRANCH=none TEST=make Change-Id: I93b74e79188bd0cc36c8b48e552230ae0d6f593a Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-24soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik
This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24mb/google/guybrush: configure eSPI mux on psp_verstageKangheui Won
Temporarily set eSPI mux in verstage_mainboard_early_init. Ideally cezanne code should have common function to do this and mb-specific code would just call it, but for now PCI access doesn't work in the PSP so we can't do it. AMD team confirmed that the current PSP doesn't configure LPC so we don't have to disable LPC when configuring eSPI mux so we can temporarliy skip the LPC part here. BUG=b:183149183 TEST=boot guybrush with psp_verstage Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-24mb/google/cherry: Implement regulator interfaceRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iab58edd019ccf9130e96fae55f147ab20cd0f45b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55751 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24mb/google/cherry: Initialize DPM in romstageRyan Chuang
Add initialization of DPM drvier used by DRAM calibration test. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I8bd10864267dfa4db8528d40483eccee2d05c1d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24mb/google/cherry: Add mt6360 driver for PMIC accessRyan Chuang
Add initialization of mt6360 drvier used by DRAM calibration test. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Id74835d8395afac9e7e2c987a0a033f1b524fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23mb/google/guybrush: Indicate the presence of ACP DMICKarthikeyan Ramasubramanian
In order to enable ACP DMIC hardware runtime detection, indicate that ACP DMIC is present. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method is populated in the ACP device. Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/google/guybrush: Add guybrush specific AMDFW config fileMartin Roth
This takes the "generic" AMD firmware config file from the cezanne directory and removes pieces unnecessary for guybrush. Removed: - PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin - PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin - PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin - DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin - PSP_MP2CFG_FILE MP2FWConfig.sbin BUG=b:187103438 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a0ed1edd7616a890f906b7f3e4a7d364758ca47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23mb/google/dedede/var/magolor: Enable weida touchscreen for magisterDavid Wu
Add weida touchscreen support for magister. BUG=b:191633024 BRANCH=dedede TEST=Build and verify that touchscreen works on magister. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3de6a84d2d58ef87f0ae13e8a117a980a0210ac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Randy Lai <randy.lai@weida.corp-partner.google.com>
2021-06-23mb/google/dedede/var/sasukette: Change ELAN touchpad driverZhi Li
Use drivers/i2c/hid can't update firmware by kernel update script, so change to drivers/i2c/generic. BUG=b:188602529 BRANCH=dedede TEST=can update ELAN touchpad firmware(277.0_1.0) by kernel script Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55248 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/google/guybrush: Only enable early port80s if using psp_verstageMartin Roth
PSP_Verstage will enable eSPI early in the boot sequence. If the platform isn't using psp_verstage, the system can hang on the first port 80h postcode that comes out because they aren't routed to an active device until eSPI is configured. BUG=b:191370340 TEST=Build without PSP_Verstage, verify system doesn't hang. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I37fbb251cd79609b856c4480ca29ce94b08897d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55738 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/google/brya/variants/primus: set up gpioMalik_Hsu
Set the GPIO configuration of primus BUG=b:190643562 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I405561ae8a44d95ffdc526241f9c52761f67ed35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-22drivers/i2c: sx9310: fix overridetree.cbGwendal Grignou
An error in script did not set the attribute properly: - Entry CS0 is not used as sensor, but as ground, - Entry CS1 is used as the startup sensor. This fixes a regression caused by commit 689c25b9d6 (drivers/i2c: sx9310: Replace register map with descriptive names) EQ=b:173341604 BRANCH=volteer Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I92c01209031e9a917d95b1cb2537b0ce7b93e66d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51893 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ica2f2856000c8dcbf4d23b7b4a3c479dc7d4862b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-06-21mb/google/guybrush: Add devfn macros for devices on GPP bridgeKarthikeyan Ramasubramanian
Add devfn macros for some peripheral devices that are attached to PCIE GPP Bridge. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I7c5433dff2329f13c282908e2b848405819347ff Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-21mb/google/dedede/var/blipper: Configure Acoustic noise mitigation UPDsZanxi Chen
Enable Acoustic noise mitigation for blipper and set slew rate to 1/8 which is calibrated value for the board. BUG=b:187760191 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I187702c23712416eaaaaf1e210dcfc6b2c560041 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-21mb/guybrush: Probe FW_CONFIG for FP_PRESENTRob Barnes
Only enable fingerprint device when FP=FP_PRESENT in FW_CONFIG. BUG=b:186685292 TEST=Boot guybrush, no "EC failed to respond in time" error Change-Id: Ifaea9e23e6cdfdae024464ff36c1520b8ad05e50 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-19mb/google/dedede: Configure CBI EEPROM WPAseda Aboagye
On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write protect signal is decoupled from the hardware write protect signal. Instead, we'd like for it to mirror the software write protect status. This commit simply checks the software write protect status of the SPI flash and sets the CBI EEPROM write protect if it's enabled. To prevent changing the WP signal at run-time, the GPIO configuration is also locked down after the level has been set. If HW WP is deasserted, the CBI EEPROM WP will be deasserted as well. BUG=b:191189275,b:184592299 BRANCH=None TEST=Build and flash lalala, disable SW WP by running `flashrom -p host --wp-disable` from a root shell and verify that the GPIO is asserted after a reboot. Export the gpio via sysfs and verify that attempting to change the value of the GPIO is futile. Enable SW WP via `flashrom -p host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs and verify that attempts to change the GPIO value are futile. localhost ~ # iotools mem_read32 0xfd6e08d0 0x44000200 localhost ~ # cd /sys/class/gpio/ localhost /sys/class/gpio # echo 217 > export localhost /sys/class/gpio # cd gpio217/ localhost /sys/class/gpio/gpio217 # echo out > direction localhost /sys/class/gpio/gpio217 # cat value 0 localhost /sys/class/gpio/gpio217 # echo 1 > value localhost /sys/class/gpio/gpio217 # cat value 1 localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0 0x44000200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-18mb/google/cherry: enable display supportJitao Shi
To enable display, we have to: 1. Configure panel power and backlight 2. Configure eDP driver BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ida6c157a6a3bd904d3fa3dd2001385ced34f7711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55574 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18mb/google/bry: remove GSC option as it's not usedYH Lin
BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I932178dc395a4a96682a2e2076131feb3342aa52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55597 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18google/trogdor: change board ID detect to tristate solution.Sheng-Liang Pan
change binary board ID to tri-state mode. BUG=b:190250108 BRANCH=None TEST=emerge-trogdor coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I79d1212abc227341be126969ef32e76a635cbdaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55563 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/guybrush: Add helpers for cbi fw_config settingsMartin Roth
Turn on CBI and add helper functions for determining the board configuration from the firmware config settings in CBI. BUG=b:187316460 TEST=Built Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/brya/brya0: Update GPIO tables based on new board revTim Wawrzynczak
This change also restores GPIOs to their proper settings for prior board revs. BUG=b:189362981 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325 Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/dedede/var/kracko: Configure I2C high and low timesTony Huang
Configure I2C high / low time in device tree to ensure I2C CLK runs under I2C_SPEED_FAST (400 kHz). Touchpad: 387.7kHz Touchscreen: 389.4kHz Audio: 387.6kHz P-sensor: 372.5kHz BaUG=b:178092096 BRANCH=dedede TEST=Build and EE check after tuning I2C clock is under 400kHz Change-Id: I4f6bdd3802cd94671325a89458cde981a2ffa929 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17mb/google/cherry: fix GPIO polarity for TPM interruptRex-BC Chen
The GPIO_GSC_AP_INT itself is active low, but the payloads will create the IRQ using its eint driver, which is active high. BUG=b:188392736 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie39f3b9a5dbe15057ef3e96f6c99211949692003 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-17mb/google/cherry: Add display configurationRex-BC Chen
BUG=b:189985956 Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I2b68f6342e7d46d90ea0e7aef9a01ecfd35f8fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-17soc/amd/picasso: introduce and use devicetree aliases for UART0-3Felix Held
Since the default state of the MMIO UART devices in the chipset devicetree is off, the mainboard devicetree entries that disable MMIO UART devices are removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/dedede: Create cappy variantZhi Li
Create the cappy variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:190515828 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Id5a3b0cb475ee77a9f62523d8322a5e4123ce3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/55451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17mb/google/dedede/var/pirika: Add camera supportAlex1 Kao
Add camera support in devicetree. BUG=b:190797339 BRANCH=None. TEST=built pirika firmware and verified camera function is OK. Change-Id: I66ded32105f3166e2faec3ea5dcfb93c29822366 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55450 Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/brya: Configure WWAN GPIO earlyVarshit Pandya
In order to meet timing requirement of WWAN reseting it in early GPIOs and asserting Reset GPIO in ramstage BUG=b:180166408 TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/*: Fix some indirect includesKyösti Mälkki
Fix build failures in the case <vc/.../chromeos.h> is removed. Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16mb/google/zork: enable UART0 in devicetreeFelix Held
This a mainly a preparation for adding the MMIO UART devices to the chipset devicetree. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16soc/amd/picasso: introduce and use devicetree aliases for I2C2&I2C3Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16broadwell boards: Use Haswell hostbridge.aslAngel Pons
Use hostbridge.asl from Haswell instead of Broadwell. Both files are equivalent. Then, drop the now-unused hostbridge.asl from Broadwell. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-14mb/google/volteer/var/collis: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I18ee085cde0570ef278ea3869be30471ed04e3db Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/eldrid: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Icfde6b57ff5f6e49ff7804eff6e6a5819bb784bc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/volet: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ib0858afa1b5dc9de9db87485d3e0bf6032416746 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/elemi: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I19b5e1c4beebbc1ebd3d2e30bc22e8c890aaf78f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/copano: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I7d35c284b88b8828d31fff9ccafeb914542b0837 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/voema: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: If8c253236051f6d170fab444cfc166e5d2ed7bc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/drobit: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I49f7b1b69c3c3ab5593c7230d8f631a3b54c9c9d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/terrador: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I1214246bb1318869e9b6f57cb6a7e74bbe6574cc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/delbin: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ifb6b5b14cec9e6f7c68aa9b01621fdb21c885552 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/volteer2: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I07be950096aef42dbf4f067134e56c5849dfa02d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14mb/google/volteer/var/voxel: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ia7db2d0a1fff98d1cfb8e7e979c0a81b9f3d0e9e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14mb/google/volteer/var/baseboard: change GPP_A11 to PLTRSTNick Vaccaro
The system will hang when resuming from S3 if the SSD reset gpio is not reset early enough. Change GPP_A11 in baseboard to PLTRST to avoid an S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ia78d813cb6bc689b07e8d8ead1ade6e77f925ce1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14soc/intel/broadwell/pch: Replace ACPI device NVSAngel Pons
The same functionality can be provided through a runtime-generated SSDT. The remaining parts of device NVS are removed in a follow-up. Since the SSDTs are only loaded after the DSDT (if loaded at all), using SSDT-provided objects outside method bodies is not possible: the objects are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing to this, the operation regions used by the _PS0 and _PS3 methods need to be moved into the SSDT, as they depend on the SSDT-provided BAR1 values. Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with no errors and contains expected values. Linux does not complain either. Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/voema: Reduce stop delay time to 150ms for ELAN TSDavid Wu
Set register "generic.stop_delay_ms" to 150 to reduce power resume time. BUG=b:185308246 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Idd90191ee7ecbbc544121dc0b93101bea64f0e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54275 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/google/volteer/variants/elemi: Include SPD for MT40A512M16TB-062E:RWisley Chen
Add SPD support to elemi for MT40A512M16TB-062E:R BUG=b:190020997 TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-bootimage Change-Id: I548ea2ec01dd0a43442a691cf870c2bc1b58bc74 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-14mb/google/volteer/var/trondo: Update gpio settingsDavid Wu
This is the same settings as voxel. BUG=None TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage Verify that the image-trondo.bin is generated successfully. Change-Id: I04df68ce1683fa32195df1a93f5bde2e3efe6090 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-14mb/google/brya: Create gimble variantMark Hsieh
Create the gimble variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:190334274 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GIMBLE Change-Id: If425571d95b3b20910f890428fb5726ebad2fdf4 Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55300 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/google/hatch: Create scout variantJeff Chase
Create the scout variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:187080143 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_SCOUT Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: I3be9d2d30821c2c9132ed94c9faf1f33b62bbc7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-06-14mb/google/guybrush: Update memory configurationIvy Jian
Regenerate SPD for MT53E1G32D2NP-046 WT:B with correct value of ranks. BUG=b:190692797 TEST=Build and boot to OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Icee095c7114f1d6dd960f2134db3816b367bf987 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-13mb/google/cherry: get SKU ID from EC (CBI)Rex-BC Chen
The SKU ID for Cherry is retrieved via CBI interface. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Icefa016c2e5f68bd194f76d2252856835c65b8e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-06-12mainboard/google/brya: Enable software syncBoris Mittelberg
This change removes the GBB flag that disables SW sync BUG:184229267 TEST:manually running chromeos-firmwareupdate Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ie8b759a0cdb0c3a0a6458f64c16216459f076e27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55400 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12mb/google/volteer/var/volet: remove USB4_GEN3 configuration for volet.Sheng-Liang Pan
volet don't support usb4, remove it to prevent USBC(P0) issue. BUG=b:189740531 TEST=build and verify USB(P0) disaply out normal Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia78c7cee76ec2e3a5334ad8805a0d45616aade93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55344 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11mb/google/guybrush: Add EC_HOST_EVENT_HANG_DETECT to wake maskRob Barnes
Add EC_HOST_EVENT_HANG_DETECT to S3/S5/S0ix wake mask. This event is sent when the EC detects the AP didn't fully enter a sleep state. BUG=b:186571086 TEST=Trigger hang detect while AP is in S0ix, AP wakes from S0ix Change-Id: I09ccf609fc453c19b4fb1ddaa5a0c86d7a85aad1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-11mb/google/brya: Update PMC Descriptor for Alder lake A0(0x906a0) siliconSridhar Siricilla
The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. coreboot logs appear as below with this patch: On First boot after flashing the image: coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)... CPU: Genuine Intel(R) 0000 CPU: ID 906a0, Alderlake Platform, ucode: 0000001a .. FMAP: Found "FLASH" version 1.1 at 0x1804000. FMAP: base = 0x0 size = 0x2000000 #areas = 32 FMAP: area SI_DESC found @ 0 (4096 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Erasing flash addr 0 + 4 KiB Update of PMC Descriptor successful, trigger GLOBAL RESET Next boot after GLOBAL RESET: coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)... .. FMAP: area SI_DESC found @ 0 (4096 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Update of PMC Descriptor is not required! VBOOT: Loading verstage. .. CBFS: Found 'fallback/verstage' @0x2264c0 size 0x16b08 in mcache @0xfef84d38 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10mb/google/guybrush: Move variant_has_fpmcu() after eSPI initMartin Roth
Currently variant_has_fpmcu() is called very early in bootblock, before eSPI is initialized. When checking CBI for its presence, that causes an error and nothing else can be read from CBI in bootblock. Moving it slightly later in bootblock doesn't hurt anything from a timing standpoint, and allows CBI to be read. BUG=None TEST=See CBI get read and the FPMCU field read correctly. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6de44119e92c8820b266f9f07287706c7d4eb505 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10soc/intel/tigerlake: Move MAX_CPUS to KconfigAndy Pont
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS value within src/soc/intel/*/Kconfig. Move the definition there for Tiger Lake and remove from the mainboard Kconfig files. Signed-off-by: Andy Pont <andy.pont@sdcsystems.com> Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10mb/google/dedede/var/pirika: Support Realtek audio codec ALC5682I and ↵Alex1 Kao
speaker L/R Add Realtek audio codec ALC5682I and speaker L/R the same way as in waddledee BUG=b:188446060 BRANCH=dedede TEST=Boot to check ALC5682I and speaker L/R are functional Change-Id: I8173ffbfb1a8f18978a5e35c69972d4a6d8cb04a Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54529 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10mb/google/brya: Add variant GPIO override functionsTim Wawrzynczak
Provide functions to allow for variants to override only a few pads from the baseboard table. BUG=b:189362981 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3ae6c11ca8614d523f3402f1c1abb7c82124e473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 15:03:53 +0000