mb/google/volteer/var/chronicler: add chronicler memory configuration and gpio and devicetree settings

add memory configuration for chronicler,
based on schematic and gpio table, update gpio and devicetree settings for chronicler.

BUG=b:187318819
BRANCH=None
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
verify bootable with chronicler

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Id5524b97a236dcc64d18ab1cd2ce13f6bb2d998f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55340
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 563 insertions, 14 deletions

diff --git a/src/mainboard/google/volteer/variants/chronicler/Makefile.inc b/src/mainboard/google/volteer/variants/chronicler/Makefile.inc
new file mode 100644
index 0000000000..b0bfc567ff
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/chronicler/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/chronicler/gpio.c b/src/mainboard/google/volteer/variants/chronicler/gpio.c
new file mode 100644
index 0000000000..2c61cc2cd3
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/chronicler/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A7  : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
+	PAD_CFG_GPO(GPP_A7, 1, DEEP),
+	/* A8  : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_A8, 0, DEEP),
+	/* A10 : I2S2_RXD ==> EN_SPKR_PA */
+	PAD_CFG_GPO(GPP_A10, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A18 : DDSP_HPDB ==> HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+	/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+
+	/* B2  : VRALERT# ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+	/* B3  : CPU_GP2 ==> PEN_DET_ODL */
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+	/* B4  : CPU_GP3==> EN_PP3300_EMMC */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* B9  : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, DN_20K),
+	/* C3  : EMMC_PE_WAKE_ODL*/
+	PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+	/* C4  : EMMC_PERST_L*/
+	PAD_CFG_GPO(GPP_C4, 1, DEEP),
+
+	/* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */
+	PAD_NC(GPP_C5, DN_20K),
+	/* C10 : UART0_RTS# ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* C20 : UART2_RXD ==> FPMCU_INT_L */
+	PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+	/* D6  : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */
+	PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
+	/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+	/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_D17, 1, DEEP),
+
+	/* E1  : SPI1_IO2 ==> PEN_DET_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+	/* E2  : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	/* E3  : CPU_GP0 ==> USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	/* E4  : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	/* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+	/* E7  : CPU_GP1 ==> USI_INT */
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+	/* E8  : SPI1_CS1# ==> SLP_S0IX */
+	PAD_CFG_GPO(GPP_E8, 0, DEEP),
+	/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+	/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+	/* E18 : DDP1_CTRLCLK ==> NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E20 : DDP2_CTRLCLK ==> NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : DDP2_CTRLDATA ==> NC */
+	PAD_NC(GPP_E21, NONE),
+
+	/* F7  : GPPF7_STRAP ==> GPP_F7_STRAP */
+	PAD_NC(GPP_F7, DN_20K),
+	/* F8  : I2S_MCLK2_INOUT ==> HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
+	/* F11 : THC1_SPI2_CLK ==> NC */
+	PAD_NC(GPP_F11, NONE),
+	/* F12 : GSXDOUT ==> NC */
+	PAD_NC(GPP_F12, NONE),
+
+	/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+	PAD_CFG_GPO(GPP_F13, 1, DEEP),
+	/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
+	PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+
+	/* H0  : GPPH0_BOOT_STRAP1 */
+	PAD_NC(GPP_H0, DN_20K),
+	/* H1  : GPPH1_BOOT_STRAP2 */
+	PAD_NC(GPP_H1, DN_20K),
+	/* H2  : GPPH2_BOOT_STRAP3 */
+	PAD_NC(GPP_H2, DN_20K),
+	/* H3  : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H3, 1, DEEP),
+	/* H10 : SRCCLKREQ4#  ==> WLAN_PERST_L*/
+	PAD_CFG_GPO(GPP_H10, 1, DEEP),
+	/* H11 : SRCCLKREQ5# ==> EMMC_CLKREQ_ODL*/
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* H16 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+	/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+
+	/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+	/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+	/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+	/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+	/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* C8 : UART0 RX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9 : UART0 TX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+
+	/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+	/* assert reset on reboot */
+	PAD_CFG_GPO(GPP_A13, 0, DEEP),
+	/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+	/* B2  : VRALERT# ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+	/* B4  : CPU_GP3==> EN_PP3300_EMMC */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+
+	/* B11 : PMCALERT# ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+	/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+	/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+	/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+	/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+
+	/* H10 : SRCCLKREQ5# ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H10, 1, DEEP),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/volteer/variants/chronicler/memory.c b/src/mainboard/google/volteer/variants/chronicler/memory.c
new file mode 100644
index 0000000000..8ec6996d11
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/chronicler/memory.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_DDR4,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc b/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc
index b0ca2223a8..809572d790 100644
--- a/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc
+++ b/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc
@@ -1,5 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 ## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
 
-SPD_SOURCES = placeholder.spd.hex
+SPD_SOURCES =
+SPD_SOURCES += ddr4-spd-2.hex      # ID = 0(0b0000)  Parts = H5ANAG6NCMR-XNC
+SPD_SOURCES += ddr4-spd-7.hex      # ID = 1(0b0001)  Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE
+SPD_SOURCES += ddr4-spd-1.hex      # ID = 2(0b0010)  Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, MT40A512M16TB-062E:R, K4A8G165WC-BCWE
+SPD_SOURCES += ddr4-spd-9.hex      # ID = 3(0b0011)  Parts = H5ANAG6NCJR-XNC, K4AAG165WB-BCWE
diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt
index fa247902ee..bc65b38b33 100644
--- a/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt
+++ b/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt
@@ -1 +1,10 @@
 DRAM Part Name                 ID to assign
+H5ANAG6NCMR-XNC                0 (0000)
+MT40A1G16KD-062E:E             1 (0001)
+K4AAG165WA-BCWE                1 (0001)
+H5AN8G6NDJR-XNC                2 (0010)
+MT40A512M16TB-062E:J           2 (0010)
+MT40A512M16TB-062E:R           2 (0010)
+K4A8G165WC-BCWE                2 (0010)
+H5ANAG6NCJR-XNC                3 (0011)
+K4AAG165WB-BCWE                3 (0011)
diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt
index e4258b530d..b6833204f4 100644
--- a/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt
+++ b/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt
@@ -1,11 +1,9 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.inc and dram_id.generated.txt by running the
-# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
-# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
-
-# Part Name
+H5ANAG6NCMR-XNC
+MT40A1G16KD-062E:E
+K4AAG165WA-BCWE
+H5AN8G6NDJR-XNC
+MT40A512M16TB-062E:J
+MT40A512M16TB-062E:R
+K4A8G165WC-BCWE
+H5ANAG6NCJR-XNC
+K4AAG165WB-BCWE
diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
index 32204c58e7..c5a99e78cd 100644
--- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
@@ -1,6 +1,285 @@
 chip soc/intel/tigerlake
 
+	register "TcssAuxOri" = "1"
+	register "DdiPort1Hpd" = "0"
+	register "DdiPort2Hpd" = "0"
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
+
+        # Enable EMMC PCIE 5 using clk 5
+        register "PcieRpEnable[4]" = "1"
+        register "PcieRpLtrEnable[4]" = "1"
+        register "PcieRpHotPlug[4]" = "1"
+        register "PcieClkSrcUsage[5]" = "4"
+        register "PcieClkSrcClkReq[5]" = "5"
+
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | WLAN, SAR0                |
+	#| I2C3              | Camera, SAR1              |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50),
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 160,
+				.scl_hcnt = 75,
+				.sda_hold = 36,
+			},
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+                        .speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 75,
+				.sda_hold = 36,
+                        },
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 75,
+				.sda_hold = 36,
+                        },
+
+		},
+	}"
+
+	# Disable M.2 WWAN
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
+
+	# Type-A / Type-C C1
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+
+	# Type-A / Type-C C0
+	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
+
 	device domain 0 on
-	end
+		device ref dptf on
+			chip drivers/intel/dptf
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,	CPU,	       95, 5000),
+					[1] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_1, 55, 6000),
+					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_0, 70, 6000),
+					[3] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_2, 52, 6000),
+					[4] = DPTF_PASSIVE(CPU,	TEMP_SENSOR_3, 60, 6000)}"
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,	       105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,	80, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,	70, SHUTDOWN)}"
+
+				## Power Limits Control
+				# 3-17W PL1 in 200mW increments, avg over 28-32s interval
+				# PL2 set to 60W, avg over 28-32s interval
+				register "controls.power_limits" = "{
+					.pl1 = {.min_power = 3000,
+						.max_power = 17000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 200,},
+					.pl2 = {.min_power = 60000,
+						.max_power = 60000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 32 * MSECS_PER_SEC,
+						.granularity = 1000,}}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = { 100, 6500, 220, 2200, },
+					[1] = {  90, 5900, 180, 1800, },
+					[2] = {  80, 5400, 145, 1450, },
+					[3] = {  70, 4900, 115, 1150, },
+					[4] = {  63, 4600,  90,  900, },
+					[5] = {  58, 4300,  55,  550, },
+					[6] = {  54, 4100,  30,  300, },
+					[7] = {  50, 3800,  15,  150, },
+					[8] = {  45, 3500,  10,  100, },
+					[9] = {   0,    0,   0,   50, }}"
 
+				# Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on end
+			end
+		end # DPTF				0x9A03
+
+		device ref north_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 2)"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 2)"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref south_xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device ref usb2_port2 on
+							probe DB_USB USB3_ACTIVE
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(3, 1)"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(4, 1)"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device ref usb3_port2 on
+							probe DB_USB USB3_ACTIVE
+						end
+					end
+				end
+			end
+		end
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/generic
+				register "hid" = ""MLFS0000""
+				register "desc" = ""Melfas Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+				register "probed" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "5"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+				register "enable_delay_ms" = "55"
+				register "has_power_resource" = "1"
+				device i2c 34 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98357A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+				register "sdmode_delay" = "5"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp5 on end
+		device ref pmc hidden
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "9"
+						register "usb3_port_number" = "1"
+						# SBU & HSL follow CC
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "4"
+						register "usb3_port_number" = "2"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end # PMC
+	end
 end