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This feature was originally present and then dropped, but turns out
that users prefer it. Set the backlight to 50% in romstage, back to
zero in ramstage; skip enabling on the S3 resume path.
TEST=build/boot google/eve, verify keyboard backlight turns on/off
as expected.
Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Move the jack detect GpioInt resources under the codec (where they
belong), but also leave a copy under LPEA for since the Linux drivers
(incorrectly) require them there. Add pin list for Windows' SST driver.
Adapted from the Intel ValleyView edk2 ACPI reference code.
TEST=build/boot Win11, Linux on google/swanky; verify audio functional
OOTB under Linux, under Windows with coolstar's drivers.
Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
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- add HRV and GpioIO for coolstar's windows drivers
- fix interrupt type for TI jack detect switch
TEST=build/boot Win11, Linux on google/cyan; verify audio working
OOTB under Linux, under Windows with coolstar's audio drivers.
Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby.
The wake issue either needs to be fixed, or S1 should not be advertised
as a capability in the ACPI table.
Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not
supported on Skyrim devices. This results in 'standby' being removed
from /sys/power/state.
BUG=b:263981434
TEST=suspend_stress_test
TEST=frostflow-rev2 ~ # cat /sys/power/state
freeze mem
Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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C1-state auto demotion feature allows hardware to determine C1-state
as per platform policy. Since platform sets performance policy to
balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter PC2 and lower
state in camera preview case and save platform power.
Note: C1 demotion heuristics used EPB parameter to balance between power
and performance, i.e. low threshold when EPB is low in-order to get C1
demotion faster and vice-versa. ChromeOS operates at default EPB=0x7
(low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits
than expected (similar to AC mode) and losing power respectively.
BUG=b:286328295
TEST=Code compiles and correct value of c1-state auto demotion is
passed to FSP. Also verified PC residency improvement ~10% in
camera preview case.
Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add support for SD card reader GL9750 and RTS5227S
BUG=b:284273384
TEST=emerge-rex coreboot
Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add the new memory support:
Samsung K4U6E3S4AB-MGCL
BUG=b:294151054
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \
src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add pirrha supported memory parts in mem_parts_used.txt, generate
SPD IDs for them.
1. K3KL8L80CM-MGCT (Samsung)
2. K3KL6L60GM-MGCT (Samsung)
BUG=b:292134655
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage
Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add more details to instruct future boards/models implementers regarding
how GFX devices should be added.
If HDMI and DP connectors are enumerated by the kernel in
/sys/class/drm/ then corresponding GFX device should be added to ACPI.
It is possible that some connectors do not have dedicated ports, but
still enumerated.
The order of GFX devices is DDIA -> DDIB -> TCPX.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Add override devicetree based on schematics(ver. 20230714).
BUG=b:290248526
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This makes sure google/ovis don't get a random mac address on boot.
Additionally, program the LAN WAKE GPIO properly as per the Ovis
schematics dated July'23.
BUG=b:293905992
TEST=Verified on google/ovis that able to get the fixed MAC address across the power cycles.
Change-Id: I699e52e25f851de325f96ef885e04d15ca64badd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76872
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AB-MGCL.
BUG=b:293240969
TEST=emerge-dedede coreboot
Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Configure GPIOs based on schematics and confirm with EE.
BUG=b:290248526
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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1. Joxer uses dptf.dv to distinguish 6W/15W by setting OEM variable.
2. Update passive policy and critical policy.
BUG=b:285477026, b:293540179
TEST=emerge-nissa coreboot and check the OEM variable.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
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Currently, S0iX test is failing because S0i2 susbstate is blocked.
Enable RTD3 for SSD to unblock S0i2.2 substate residency.
BUG=none
TEST=Screebo can enter into S0iX.
S0iX substate residency w/o this CL -
```
Substate Residency
S0i2.0 0
S0i2.1 38451594
S0i2.2 0
```
S0iX substate residency w/ this CL -
```
Substate Residency
S0i2.0 0
S0i2.1 12108
S0i2.2 33878424
```
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Restrict ASPM to L1 for SD controller to avoid AERs.
BUG=b:288830220
TEST=No PCIE AER on SD controller on Screebo.
w/o this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
~ # lspci -s 02:00.0 -vvv | grep -i aspm
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
~ # dmesg | grep -i -e "pci.*error"
[ 0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[ 0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[ 0.735258] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000
[ 0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[ 1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[ 1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[ 1.548894] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000
[ 1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0
```
w/ this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
~ # lspci -s 02:00.0 -vvv | grep -i aspm
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
~ # dmesg | grep -i -e "pci.*error"
```
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H54G56CYRBX247
2. H9HCNNNCPMMLXR-NEE
3. MT53E1G32D2NP-046 WT:B
4. K4UBE3D4AB-MGCL
5. K4UBE3D4AA-MGCR
BUG=b:290811418
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Change-Id: Ib7f23dc3604fe1869772d92c9d7b8cc32ed9bbb9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch chooses to show the early splash screen which is an
OEM feature. The current implementation is relying on the Intel
FSP GFX PEIM to perform the display initialization.
Having this feature allows the platform to show the user notification
with 500ms since boot compared to traditional scenarios where first
user notification is coming from kernel (typically ~3sec+ after cpu
reset). Eventually this feature will help to improve the user
experience while booting Intel SoC platform based chromeos devices.
BUG=b:284799726
TEST=Able to see the early splash screen on google/rex.
Change-Id: I399ddb6618e774302200e8a87629647ba070d080
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76361
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These devices are not present/used on CYAN boards.
Change-Id: I012b49562c2b932822823537032e2265901ddc81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76799
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Ovis4ES variant supports only ESx SoCs. Existing Ovis variant will
support QS SoCs.
BUG=b:293409364
TEST=util/abuild/abuild -p none -t google/rex -b ovis4es -x -a
TEST=util/abuild/abuild -p none -t google/rex -b ovis -x -a
Change-Id: Iacf5ef6d3dfee8838fe13e68b254a84e4a6cf200
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76789
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch changes the `EC CONx Mapping` to fix the hot-plug issue
where attaching a device to USB-C port C1 can affect the USB-C
display over port C2.
Note: `PMC MUX Mapping` remains unchanged to reflect the underlying
board design where the physical MUX has swapped between C1 and C2
USB-C port.
Before:
| PMC MUX Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
| EC CONx Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
Physical Mapping between EC and SoC as below:
Port C0 - EC CON0 ----> PMC MUX CON0
Port C1 - EC CON1 ----> PMC MUX CON2
Port C2 - EC CON2 ----> PMC MUX CON1
After:
| PMC MUX Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
| EC CONx Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 1 | 3 |
| USB3-Port | 0 | 1 | 2 |
Physical Mapping between EC and SoC as below:
Port C0 - EC CON0 ----> PMC MUX CON0
Port C1 - EC CON1 ----> PMC MUX CON1
Port C2 - EC CON2 ----> PMC MUX CON2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I59e2630bc0f93321cc4b734fcf3c4cf254882477
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Users report having the touchscreen as a wake device causes many
spurious wakeups due to proximity to the keyboard when the lid is
closed, so remove it as a wake source.
TEST=build/boot google/glimmer, observe no unintended wakeups when
the lid is closed.
Change-Id: Id16cabcd21afa0b373ecddd9eb3b0b8befb71576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76794
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the ACPI SSID using Google's project campfire ID for EVE, to allow
coolstar's Windows drivers to identify the device (since it uses a
generic ACPI _HID). Custom drivers are necessary under Windows since
the touchpad firmware is not fully I2C-HID compliant.
TEST=build/boot Win11 on google/eve, verify touchpad fully functional.
Change-Id: I3b8d56ff01d4cca7ba5c02f1aaab1a7049607dbc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for vell board. Please refer Intel doc#723158 for
more information.
BUG=b:293535284
TEST=build and boot vell
Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The EAPD pin needs to be enabled and set in order for the headphone
jack to work properly. It's already done for the speaker in the
beep verbs, but needs to be done for the HP jack as well in order
for output to work properly under Windows.
TEST=build/boot Win11 on LINK, verify headphone output functional
when headphones plugged in.
Change-Id: I411d7317aefc1154635c4c17ca0dc1e37c9f40f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76746
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the pirrha variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:292134655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PIRRHA
Change-Id: Idc0a4dbb467cbdb91a5ed55c5e0a9e898e775b11
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76768
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Vendor changes touchscreen firmware to use hid method instead of i2c.
BUG=b:274707912
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I8e9e0b757e337db6af3fbf3cd4fdbc0079646179
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76680
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The EC serial port on these devices is not accessible to the end user
and exposing it to the OS via ACPI serves no purpose. Debugging over
the EC serial port (via the servo interface) does not require the
ACPI exist. Drop it since it's not needed and serves no purpose.
TEST=build/boot Win11 on auron/link/slippy, verify Windows Device
Manager no longer shows an unusable COM port.
Change-Id: If453bfca8e094aa06043293bdf91a40c38cc7866
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76793
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update SX9324 register settings based on tuning value from SEMTECH.
－ Enable GPP_B5/GPP_B6
－ Enable GPP_H19 open irq
－ Adjust register reg_afe_ctrl0/reg_afe_ctrl3/reg_afe_ctrl4
BUG=b:292016304
BRANCH=None
TEST=Check register settings and confirm P-sensor function can work.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I6f15f7a7c428aee45d35830574ef84aefcae6401
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76711
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add wifi sar table for constitution
BUG=b:291859402
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I8f99c5cf486cb3e1f2825bbe3a8084f2fe57a41a
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76674
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Change the SSID to allow the correct Creative Labs Windows audio drivers
to attach (vs generic HDA audio ones) and provide full functionality.
Linux doesn't care about the SSID, so changing it has no effect there.
TEST=build/boot Windows, Linux on google/link, verify the correct
audio drivers attach under Windows, no regressions under Linux.
Change-Id: Ib5e523b07583289b0222ef156245fb0771ad1f1c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76745
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Set GPP_C6(TCHSCR_REPORT_EN) and GPP_C7(TCHSCR_INT_ODL) to NC for
non-touchscreen sku.
BUG=b:283199751
BRANCH=firmware-nissa-15217.B
TEST=build and boot to ChromeOS
Change-Id: Ie062eef24f640c3d6c4a0b4c77792e57ac3a722c
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Uldren will support internal fivr in next phase and using fw_config to
decide the board with internal or external fivr.
BUG=b:287379760
BRANCH=firmware-nissa-15217.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I8a1ac60f599f2895654946d9fa1c4e1f2657fd10
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) LP5 Memory - 2GB Micron MT62F512M32D2DR-031 WT:B
2) LP5 Memory - 2GB Hynix H9JCNNNBK3MLYR-N6E
3) LP5 Memory - 4GB Samsung K3LKBKB0BM-MGCP
4) LP5 Memory - 4GB Hynix H9JCNNNCP3MLYR-N6E
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 1 (0001)
H9JCNNNCP3MLYR-N6E 2 (0010)
BUG=b:292461498
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I02e49d60e43c4fed8356556ec194d726c30cd609
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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The patch disables PCH USB2 Phy power gating to fix display flicker
BUG=b:292403156
TEST=Verified on the defeat board
Change-Id: If0c0e655c5d32f39b90635bb3c1d13d8b6993b59
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Update Touchscreen GPIO to use the correct GPIO 90. GPIO 32 was a
copy/paste from dalboz and corresponds to the FP PWR EN on trembyle
platforms.
BUG=b:292656388
TEST=build/boot morphius
Change-Id: Ia6cdbe9195535093e68dbafedaddb70aaf73da88
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76747
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Set the cs_pi_start_high_in_ect if the DUT is using one of the two
following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to
set cs_pi_start_high_in_ect when using these parts will result in an
MRC cache failure and DUT will fail to boot.
BUG=b:292153199
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya
variant to kernel.
Change-Id: I36040139b959c85c3ac220a34574caa12ca6c5fe
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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With currently set default PSP_SOFTFUSE_BITS for phoenix SoC,
the non-serial build does not boot on Myst.
Override PSP_SOFTFUSE_BITS by disabling SPIConfig to also get
the non-serial build booting.
The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA).
BUG=b:292489356
TEST=Flash image-myst.bin, verify that it's able to boot on Myst
proto0.
Change-Id: Id4472fd85fdefcafb8378199dbaa054fab8b3274
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76713
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: Ie1d882cac90211541a636d2dab297c343a12d66d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76743
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: I61912fd6db9eb4b8d202ab633b8c7ca5913e759f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for redrix board. Please refer Intel doc#723158 for
more information.
BUG=b:292435264
TEST=build and boot redrix
Change-Id: I34d10c763f4710d2c5678704320fd1cc8d8b6287
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76670
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Camera LED will blink several times as sensor is being probed during
kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:292173903
TEST=Build and boot on Yavilly EVT unit. Verify & observe Camera LED
blinking behavior.
Change-Id: Ic3e3439dc9313325189761b277e1a3bd1c1d9418
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add pujjo new supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Hynix H58G56BK7BX068
2. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
3. Micron MT62F1G32D2DS-026 WT:B
BUG=b:292452868
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia123a1cfd93a5e08ab0ba65f1d9be240d60ff356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76672
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a new variant screebo4es.
The new variant will support only ESx samples. The existing rex
variant will support the QS samples.
BUG=b:292280656
TEST=Able to build google/screebo4es board and boot on target
hardware.
Change-Id: If77b4a773bee3633008d39c1886b61869c9618de
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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BUG=b:290894460
TEST=`emerge-rex coreboot chromeos-bootimage`
then check variant name with image*.bin.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I8f739485dbaab074f57eaa4dacc9f228a3f4aa14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76667
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable the APOB cache for only Myst, and re-enable APOB for other
Phoenix SOC mainboards.
BUG=b:290763369
TEST=verify APOB cache is disabled
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Mapping to the fw_config of AUDIO_AMP in dedede,
and set new AUDIO_AMP configuration of ALC5650 as value 4.
BUG=b:284060672
BRANCH=dedede
TEST=build pass
Change-Id: Ic3dccd09d3ba1619cce2ac0d5f123badbeeaccdc
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch increases the `tcc_offset` to reduce the TCC
(Thermal Control Circuit) activation temperature to avoid running
into abrupt power off during power cycle tests.
On Intel processors, the core frequency can be by an HW agent when
the current temperature reaches the TCC activation temperature.
The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants).
However, this patch adjusted the TCC by specifying an offset in
degrees C (i.e., using `tcc_offset` from variant override device tree).
Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats.
BUG=b:283008762
TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown.
Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:290985698
BRANCH=firmware-volteer-13672.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I87173f93d0e47baa816d15dad0777007342b4fdb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value
for variants created using google/rex model.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples.
BUG=b:290732344
TEST=Able to build google/rex4es board and boot on target hardware.
Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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This patch creates a rex model so that other variants developed using
`rex` baseboard are easy to land without duplicating the config
selection.
So far, `rex0` and `rex_ec_ish` are developed using the `rex` model.
The plan is to extend the support for `rex4es` and `rex4es_ec_ish`
variants.
TEST=Able to build and boot google/rex.
Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Follow baseboard Rex to make GPIO changes
BUG=b:286187821
TEST=Ability to enable and disable WIFI function in OS.
Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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This supports a brand new I2C driver that is designed specifically
for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU
is an i2c-compatible interface, but AFAIK only Link has touch devices
attached in this way.
On Windows, the PCIe device for the IGP is owned by the Intel
proprietary driver, hence a separate ACPI device has to be added for
the I2C driver arbitrator to attach to. The MMIO method is used instead
of _CRS so that Windows does not try to assign ownership of the
resource to our device (even though we're using the MMIO registers at
the same time as the IGP driver).
Even though in theory 2 drivers accessing the same MMIO may cause
problems, in testing, there has been no issues with
sleep/wake/hibernate, updating/installing/uninstalling the IGP driver,
or changing display resolutions with the i2c driver attached.
The arbitrator is necessary as well, since even though there are
multiple i2c buses, the MMIO registers are shared. Hence a shared lock
is required for i2c access across the buses.
The original Sleep Button devices are preserved for Linux due to the
completely custom and non-standard implementation of the Windows driver
in order to work around the non-standard nature of Link's hardware.
Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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In order to reduce S0ix resume time, decrease stop_delay_ms from
300ms to 200ms for Goodix GT7996F. The value source is from
https://partnerissuetracker.corp.google.com/issues/285999032#comment16.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: I2f0adadbd3d0774da03338cc0abd1639104876d9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76577
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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There is a problem of screen shake on the old panel[1]. So increase the
panel GOP component pull-down circuit size in hardware, and update the
initialization code at the same time. The new initialization code is
mainly adjusted for GOP timing. When Display sleep in, raise all GOP
signals to VGHO and then drop to GND. In order to be consistent with
the current panel model, let's rename this file.
[1]: INX old panel product number is HJ110IZ-01A-B1, and the new
panel product number is HJ110IZ-01A-B2. We have recalled the shipment
old panel.
BUG=b:270276344
BRANCH=trogdor
TEST= test firmware display pass
Change-Id: I2b2534afee1ed700c39d3c360aafd685b63ccbfb
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This patch updates the Type-C USB2/3 port mapping to reflect the mux
connection change as mentioned in previous patch
commit ee3f796200bf3baf8a1906 (mb/google/rex/var/ovis: Fix mux
change as per schematics).
Here is the correct port mapping after considering the mux swap:
+--------------------------------+-------------+---------------+
| TCSS-USB Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
+------------------+-------------+-------------+---------------+
BUG=b:289300284
TEST=Able to build and boot google/ovis to get display over Type-C1
and Type-C2 port.
Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18
BUG=b:291051683
BRANCH=none
TEST=emerge-rex coreboot
Change-Id: Ic102e42482328580c5334e6ff036b774f5002e00
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76565
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.
BUG=b:284192689
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.
Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Enable CsPiStartHighinEct to fix MRC Cache fail issue
BUG=b:279835630
BRANCH=none
TEST=Pass MRC Cache test with toolkit 1000 times
Change-Id: I25cd856785bab9c661e30e2987b43f0dc2ba9564
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.
BUG=b:281643325
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.
Change-Id: I95702e675fa3b73c7e8ee0c8625c7828d8129ea8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76355
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:290876132
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Change-Id: Id5e0ba7a4ca57e311465ba8e74105f5ee7b8ee8a
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76435
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use fw_config to separate pujjoteen5 intel wifi sar table.
BUG=b:279984381
Test=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I2e744bf0801bd7b18817a00fcbe3d0c62b8fc3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76453
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Add an initial overridetree for gothrax based on the schematic.
BUG=b:274707912
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76013
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Drivers for Pen Garage/SDCard Reader/LTE/SAR/WWAN and I2C for TPM.
BUG=b:274707912
BRANCH=None
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1203ca13bd55b8ab96ce5d323a36ffde06860fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76104
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
|
|
Change i2c[0] parameter Thd:dat = 50ns;
Change i2c[1] parameter Thd:dat = 100ns;
BUG=b:287898252
BRANCH=none
TEST=Test success by EE.
Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch disables early EC sync to avoid an idle delay (~3sec)
without a provision to notify the user about some critical task
in progress.
Doing EC sync at later stage allows us to notify using graphical msg
on screen to make user aware of the WIP task.
BUG=b:279944831
TEST=Able to perform EC sync from depthcharge on google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Change touchscreen reset_gpio GPP_C01 -> GPP_D07;
Change touchscreen enable_gpio GPP_C00 -> GPP_B17.
BUG=b:289425753
BRANCH=none
TEST=Test success by EE.
Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Create the craaskov variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:290248526
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CRAASKOV
Change-Id: I1d12f7c3d0ef7067f4530c1c69c560f9a83561f6
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
|
|
Add karis supported memory parts in mem_parts_used.txt, generate
SPD id.
1. MICRON MT62F1G32D2DS-023 WT:B
2. HYNIX H9JCNNNBK3MLYR-N6E
3. HYNIX H58G56BK8BX068
4. SAMSUNG K3KL8L80CM-MGCT
BUG=b:291018417
TEST=Use part_id_gen to generate related settings
Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The PRESERVE flag in the FMD file tells futility not to erase the
fmap partition when updating the firmware. Because of an issue on
myst right now, we want the RW_MRC_CACHE partition to be erased
when the firmware is updated.
BUG=b:290763369
TEST=None
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id586ae057b2fd6d513ddbba5e1284dea39467d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76478
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Use the proper dxio_link_hotplug_type enum values for the link_hotplug
field in the DXIO descriptors to replace the magic values in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It moves cr50_plat_irq_status() to common code and adds Kconfig
option to specify GPIO used for interrupt.
BUG=b:277787305
TEST=Build all affected platform and confirm using right GPIO
number. Tested on Skyrim.
Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=b:286803481
TEST=Make screebo suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Pujjo support WWAN EM060 device, use FW_CONFIG to handle the
power on sequence.
BUG=b:290709711
TEST=Build and check WWAN EM060 power on sequence.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I66800c75274e8e1e55d4314c82b7fcdf2a4477bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76403
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch enables PCH to CPU energy report feature which can be used
by Intel Telemetry Driver.
BUG=b:269563588
TEST=Able to build and boot google/rex and perform below check to ensure
the energy reporting is correct
w/o this cl:
# lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXX0000
w/ this cl:
#lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXXfc004
Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
The CB:76219 removed mtk_i2c_bus_init() from tps65132s_setup(), so
we should initialize I2C bus for TPS65132 in mainboard now.
BUG=None
TEST=./util/abuild/abuild -t google/geralt -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Iacf78221d2416f41467c709402b7e02e03dc5fc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
There is no PCH FIVR participant on MTL and we should remove it
in Rex.
TEST=compile ok and make sure there no TPCH device in acpi
BUG=b:290322310
Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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for saving boot time, change ramstage compression from LZMA to LZ4.
Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB.
For detail, refer below.
Existing: LZMA(55.6 ms)
8:starting to load ramstage 894,519 (0)
15:starting LZMA decompress (ignore for x86) 903,556 (9,036)
16:finished LZMA decompress (ignore for x86) 949,997 (46,441)
9:finished loading ramstage 950,179 (182)
Changed: LZ4(17.8ms)
8:starting to load ramstage 900,876 (0)
17:starting LZ4 decompress (ignore for x86) 917,650 (16,774)
18:finished LZ4 decompress (ignore for x86) 918,690 (1,040)
9:finished loading ramstage 918,849 (158)
Size impact (73KB * 3 = 219KB)
fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed)
fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed)
BUG=b:286930648
TEST= Boot to OS and check boot time
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi to function properly with the connected bluetooth devices and
wake up from low power state.
BUG=None
TEST=None
Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
|
|
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=None
TEST=Make rex platform suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The actual NVM size of camera module is 64KB; however, only 8KB is in
use to store data. This reduces the size of both NVM0 and NVM1 to 8KB
to minimize the time taken to read NVM and launch Camera preview.
BUG=NONE
TEST=Launch Chrome camera application and check the time taken to
read eeprom from camera service log and show camera preview. It takes
2 to 3 seconds to show camera preview while it takes 4 to 5 seconds
without the changes.
Before the changes:
06:21:04.204944Z OpenDevice(): camera_id = 1
06:21:07.297584Z Read camera eeprom from eeprom
06:21:08.763491Z Read camera eeprom from nvmem
After the changes:
21:37:23.923676Z OpenDevice(): camera_id = 1
21:37:24.386020Z Read camera eeprom from eeprom
21:37:24.574515Z Read camera eeprom from nvmem
Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189
Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Update eMMC DLL tuning values for improved initialization reliability
BUG=b:289763421
TEST=cold reboot stress test over 5000 cycles on Foresee and Kingston
eMMC
Change-Id: I63077b8717feecf3d50507abb188b7fadb5d6c79
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76221
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine
the memory channel configuration. The signal behavior is not proper,
hence limiting the DIMM capacity to half (only MC0 is enabled).
This patch always reports the full memory capacity as in dual channel
(both MC0 and MC1 enabled).
This change is necessary to ensure that the system reports the correct
memory capacity, even if the MEM_CH_SEL GPIO is not working properly.
BUG=b:290174538
TEST=Able to detect 32GB memory capacity while booting google/ovis.
Without this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 16183080 kB
With this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 32673664 kB
Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Since multiple GFX entry causes an ACPI error when trying to write _DOD
method multiple times, combine the GFX entry into one so that _DOD
method is written just once.
BUG=b:289854155
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I22ad70d50f1aecf8da70e8dd04a36a0a7c1c7609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76329
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This CL corrects the trigger for HID over SPI from Level to Edge.
BUG:None
TEST:Tested with I2C and SPI
Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The AW37503 is designed to supply positive/negative supply for driving
the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we
need to program the registers at boot. We program the target
positive/negative output voltage via I2C and enable the power rails by
pulling up ENP and ENN pins.
On Starmie, we need +/-6V power supply for the MIPI panel. We program
the AW37503 registers in coreboot so that kernel can control AW37503
via fixed regulators without additional settings(what we did for
TPS65132). Since we distinguish AW37503 and TPS65132 by reading the
vendor ID, we need to initialize I2C bus as early as possible.
Therefore, we move mtk_i2c_bus_init() to mainboard_init().
BUG=b:289482828
TEST=emerge-staryu coreboot chromeos-bootimage
TEST=Test the sequence the voltage
Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new kingler follower 'ponyta'.
BUG=b:290259648
TEST=make # select ponyta
Signed-off-by: cengjianeng <cengjianeng@huaqin.corp-partner.google.com>
Change-Id: I74759441957e9901bd7e5a709a2ae7d97a7cd040
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76331
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74407
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The BT VGPIOs pad config in variant of gpio.c won't be overwritten on board eventually because no matched gpios existed here.
Put BT VGPIOs in gpio_table, ensure that these were able to be overwritten.
The fix included crota and omnigul BT offload work successfully.
BUG=b:264834572
TEST=test Bluetooth offload playback/capture in SCO profile.
Change-Id: I62cecf26abd0411f7cbb0a56b8b8f0a25d370c69
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add fw_config and configurate AUX pin for MB USB Type-C.
MB USB3 doesn't have re-timer, thus have to configurate the AUX pin.
BUG=b:275335023
TEST=build pass
Change-Id: I1334dcbaec6de1707c6892efbebaf8d460ba8648
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76348
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz for starting next phase.
BUG=b:270500631
BRANCH=None
TEST=emerge-skyrim coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I0915d9b10dbfae7fff4e8874011951d1690de870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
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constitution only has one TBT port, remove tcss_dma1.
BUG=None
TEST=emerge-constitution coreboot
Change-Id: Ia4eb4371eb20e75a0f464e2b087fd2fe59569537
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Pablo Ceballos <pceballos@google.com>
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Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into
an APCB for phoenix platform.
The tool makes several assumptions:
* Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero.
* Each block is 64 bytes.
* Dimm and socket are always 0
* Unused SPD entries are zero'd
BUG=b:281983434
BRANCH=None
TEST=build, flash, boot myst
Change-Id: Ifb50287de77138170714a702ab87d56427aacfef
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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tis_plat_irq_status() function is used only by Google TPM. It should
be moved to drivers/tpm/cr50.c. The name of the function was changed
to cr50_plat_irq_status().
BUG=b:277787305
TEST=Build all affected platforms
Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AB-MGCL (Samsung)
2. K4UBE3D4AB-MGCL (Samsung)
BUG=b:289873670
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7a262ac62c24cfb43c0283c9730c177a242342e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76240
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set tcc_offset value to 20 in chipset for Thermal Control
Circuit (TCC) activation feature for meteorlake silicon.
Also, remove tcc_offset default value from rex baseboard
and variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change i2c[3] parameter to meet below timing:
t-HIGH > 600ns;
900ns > Thd:dat > 300ns.
BUG=b:286030723
BRANCH=none
TEST=Test success by EE.
Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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