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2023-02-09mb/google/brya/var/omnigul: Add SOC I2C configJamie Chen
Add SoC config and .early_init = 1 in I2C1 BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-02-09mb/google/brya/var/omnigul: Modify NVMe and UFS Storage supportJamie Chen
1. Add fw_config:STORAGE_UFS & STORAGE_NVME to switch storage. 2. rp11 off change to on. BUG:b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72090 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/skyrim/var/markarth: Override SPI flash bus speedJohn Su
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz for starting next phase. BUG=b:267539952 TEST=None Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Id46201351780bb5bc05422ff36dad6972285690e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-09mb/google/brya: Create aurash variantZoey Wu
Create the aurash variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263691099 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AURASH Change-Id: I595102778071f822c5cf69ceadeed174e5ea4836 Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72837 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815Ron Lee
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. This patch add usb_lpm_incapable config for the following variants with PS8815 retimer: - kinox MLB: C0 - volmar DB: C1 - osiris MLB: C0/C1 - mithrax DB: C1 - felwinter DB: C1 - taeko DB: C1 - gimble DB: C1 - gimble4es DB: C1 - taniks DB: C1 - marasov DB: C2 - gaelin MLB: C0/C1 - skolas DB: C1 - skolas4es DB: C1 - brya0 DB: C1 BUG=b:253402457 TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u2 disabled Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Signed-off-by: Ron Lee <ron.lee@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-08mb/google/geralt: Add support for VM18 in regulator.cSen Chu
Add regulator VM18 support to supply power for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I13bafbe10a18a18e253575fd107c9b415f28ef01 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72748 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/google/corsola: Use function to get regulator IDsLiju-Clr Chen
There might be inconsistence between regulator_id[] and `enum mtk_regulator` when we need to add new regulator IDs for Geralt. Therefore, we implement get_mt6366_regulator_id() to get regulator IDs. BUG=None TEST=build pass. Change-Id: I3d28ebf2affe4e9464b1a7c1fb2bbb9e31d64a5e Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72838 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-07mb/google/brya: Create constitution variantMorris Hsu
Create the constitution variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:267539938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CONSTITUTION Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72730 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07tree: Drop repeated wordsAlexander Goncharov
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-06mb/google/brya/var/kano: Update ELAN TS delay time to 150msDavid Wu
ELAN updated the datasheet, the HID/I2C protocol's T3 delay time is 150ms now. Modify the kano's delay time to follow the requiremnet. BUG=b:247944006 TEST=Manually checked touchscreen works after reboot and suspend. Change-Id: I42a7737060a82c0b27717f1510b8ec64abd1465a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-06soc/amd/mendocino: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Mendocino SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/cezanne: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/picasso: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Picasso SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/stoneyridge: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Stoneyridge SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Eventually the LIDS object should probably be moved to the EC's ACPI code, but that's out of scope for this patch. TEST=google/liara doesn't show ACPI errors in Linux' dmesg Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-02-05mb/google/brya/var/omnigul: Enable Cnvi BT Audio Offload featureJamie Chen
1. Enable Cnvi BT Audio Offload feature and also configure the virtual GPIO for CNVi Bluetooth I2S pads. 2. According to the SOC_GPIO_Table_20230116, Change GPIO GPP_D15, GPP_D16 to NC. BUG=b:264834572 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I4901c8cd660f2d47018e4cccdb67f666f0800423 Signed-off-by: Jamie chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72035 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-05mb/google/brya/var/omnigul: Add variant specific devicetreeJamie Chen
This variant was added without a devicetree, so add the board specific devicetree according to schematic_20230110. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-02-05mb/google/nissa/var/craask: Modify clkreq to clksrc mappingRen Kuo
NVMe PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=1,clk_req=2 in mFIT. BUG=b:265720813 TEST=build firmware and veirfy suspend function on DUT. Cq-Depend: chrome-internal:5351299 Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72051 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-05mb/google/brya/var/marasov: Turn off camera power during S0ixFrank Chu
Turn off camera power during S0ix to improve power consumption. BUG=b:265754302 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie2b300783adfc1cab30bc897d086a3674436724a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-05mb/google/skyrim/var/frostflow: Override SPI flash bus speedFrank Wu
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version of the current phase. BUG=b:260127676 TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed. Observe that the boot time improved by 100 ms compared to 66 MHz SPI flash bus speed. firmware log: SPI fast read speed: 100 MHz At 66 MHz: Total Time: 1,563,384 At 100 MHz: Total Time: 1,462,570 Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-04mb/google/skyrim: Update ASPM settings for the NVMe deviceMartin Roth
This enables L1.2 for the SSD port. link_hotplug is unused on Mendocino, so remove it while I'm here, just as code cleanup. This has no functional difference. Enabling L1.2 on other devices currently causes problems. Debug is ongoing. BUG=b:265890321 TEST=Build & boot, look at states enabled in lspci. Test device functionality. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-04mb/google/rex: Use OV13B10 sensor for Proto 1 SKUsSubrata Banik
This patch drops the WFC sensor OV8856 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor OV13B10. BUG=b:267264348 TEST=WFC MIPI cameras have been enabled using google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic785b82db4368f40d91921f29c218cf417938541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-04Revert "UPSTREAM: mb/google/rex: Enable SaGv"Subrata Banik
Enabling `SaGv` along with FSP v2473 is causing blank display issue. Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake. BUG=b:267446159 TEST=Able to see ChromeOS UI in consecutive boot. This reverts commit cbca81c5946384843197c08401c4266f45fef4a2. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-04mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:266696987 BRANCH=None TEST=Observe kernel ec panic handler run when ec panics Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-03mb/google/brya0,skolas4es,skolas: disable Tccold HandshakeSelma Bensaid
The patch disables Tccold Handshake to prevent possible display flicker issue for skolas board. Please refer to Intel doc#723158 for more information. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS on Skolas, verify upd setting. Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68636 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03mb/google/nissa/var/craask: Add DPTF settings for 15W CPURen Kuo
Add ADL-N 15W CPU thermal settings. BUG=b:265101768 TEST=emerge-nissa coreboot Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71860 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03mb/google/rex: update touchscreen report EN pin settingIvy Jian
Removed workaround since the latest schematics fixed. Power Sequencing of ELAN6918 (in ACPI) after this patch `POWER enabled -> RESET deasserted -> Report EN enabled` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-02mb/google/dedede/var/dibbi: Update devicetree and GPIO tableLiam Flaherty
Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:260934185, b:260934719 BRANCH=dedede TEST=build Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02mb/google/brya: Skip locking for GPP_F14 GPIOMaulik Vaghela
This is regarding issues observed on multiple Brya and Nissa variant such as Skolas and Nivviks. Issue is that once coreboot sets GPE_EN bit for the GPIO pin and locks it, kernel is not able to change the control bit. Hence kernel is not able to control the IRQ on the pin when required. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") This patch skips the locking for GPP_F14 to allow kernel to configure it later during reboot or shutdown as required. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas and Brya board with the patch. Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02mb/google/skolas: Skip locking for GPP_F14 GPIOMaulik Vaghela
There is an existing issue for skolas boards where board wakes up from shutdown immediately due to touchpad wake signal. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") Later issue was found to be with GPP_F14 configuration for skolas boards. While shutting down, kernel is not able to disable IRQ for touchpad due to GPE_EN register getting locked and it is preventing shutdown of the board. This patch skips the locking for GPP_F14 to allow kernel to configure it later. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas board with the patch. Nissa Bug: 234097956 Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I09cf1af1f5ab11b06073755374ee8a306984d557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72426 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/brya/var/omnigul: Add memory configAmanda Huang
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Marx Wang <marx.wang@intel.com>
2023-02-01mb/google/brya/var/omnigul: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSJamie Chen
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Omnigul variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I90ae116ccccde48792aeafaa683c7420a95c9886 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72509 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/geralt: Add USB3 HUB reset funtion to bootblockBo-Chen Chen
After powering on the device, we need to pull USB3_HUB_RST_L up to enable USB3 Hub. TEST=boot kernel from USB ok BUG=b:264841530 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31mb/google/skyrim/var/winterhold: Update DPTC settings for SMTEricKY Cheng
Follow thermal team's request on b/248086651 comment#27. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651 TEST=emerge-skyrim coreboot Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-01-30src/mainboard: Remove unnecessary space after castsElyes Haouas
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-30mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSSubrata Banik
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Marasov variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. Note: Enabling this config would introduce an additional warm reset during the cold-reset scenarios due to the function disabling of the UFS controller as results we are expecting ~300ms higher boot time (which might not be user visible because `cbmem -t` can't include impacted boot time due to in-between resets). BUG=b:264838335 TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS during boot path. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-25mainboard: Drop invalid `hyper_threading` optionAngel Pons
Drop the `hyper_threading` CMOS option from most boards, as it's most likely not working properly and causing problems. The main reasons to remove the option are: * The used enum is backwards (0 ---> Enable, 1 ---> Disable) * Platform/SoC code does not honor the `hyper_threading` option Also, remove the now-unused enum used by the `hyper_threading` option. Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-25mb/google/skyrim/baseboard/devicetree: enable mp2 deviceFelix Held
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. An equivalent change was verified on Chausie. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-22mb/google/brya: Add lp5x memory parts for CrotaTerry Chen
Update the mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign MT62F1G32D2DS-026 WT:B 4 (0100) K3KL8L80CM-MGCT 4 (0100) H58G56BK7BX068 4 (0100) BUG=b:259467147 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I204e871129a1b15d7c373d579e10a7b9ab6deabe Reviewed-on: https://review.coreboot.org/c/coreboot/+/71906 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-22Revert "mb/google/brya: Add EC mux device to brya0"Anil Kumar
This reverts commit 197d550d069f918698fa7cd8dda73e09fbfda30c. Reason for revert: breaks TBT and TypeC display on Brya0 Bug=265375098 Branch=firmware-brya-14505.B Test=Build and boot Skolas board with Brya0 image. Test TBT and TypeC display functionality. Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081 Reviewed-by: Prashant Malani <pmalani@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-20mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMSTarun Tuli
1) Update location of TGP (MAGA) to Params2[15:0] 2) Add TPPA (value of 25W) Package: ... Case (0x02) { Local0 = Buffer (0x31) { 0x22, 0x05, 0x10, 0x1C, 0x01 } CreateWordField (Local0, 0x1D, MAGA) CreateWordField (Local0, 0x19, TPPA) CreateDWordField (Local0, 0x15, CEO0) MAGA = 0x50 TPPA = 0xC8 CEO0 = 0x0200 Return (Local0) } ... BUG=b:214581372 TEST=build and verify DSDT on device Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69639 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency and hold time to meet touchpad i2c SPEC. - Frequency: 380 ~ 400 kHz - hold time : 0.3 ~ 0.9 us BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 393.7 kHz Hold time = 0.604 us Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/google/brya/var/gaelin: Add touch panel module settingMike Shih
1. Enable multiple GPIOs to support the touch panel. 2. Add I2C setting for touch panel. BUG=b:260818082, b:264812909 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Change-Id: I2b805d1960f8b4e3e27f1af02f9c4d31f973288f Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-01-19intel/meteorlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for ChromeOS platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19mb/google/skyrim/var/frostflow: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for frostflow in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259007881, b:248221908 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19mb/google/skyrim/var/markarth: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for markarth in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:263534907, b:263216451 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-01-18mb/google/brya/var/marasov: Remove wlan RTD3 supportFrank Chu
Wlan power enable pin is changed from EN_PP3300_WLAN to SLP_SUS_L. Remove unused RTD3 driver. BUG=b:263448873 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I22448a8cb28ddadb93b114c096e364980feab6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71693 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18mb/google/skyrim: Add custom amdfw.cfg file to remove fwTPMMartin Roth
Skyrim doesn't use the firmware TPM, so remove the binary from the image. Note that because this was not used, removing it doesn't change the boot time. BUG=None TEST=Boot Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia627b128c3346a2556c5306de7506519d1f2d70c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17mb/google/skyrim: Set winterhold SPI fast read speed to 100MHzMartin Roth
Winterhold runs with the SPI fast read speed set to 100MHz. This decreases boot time by roughly 100ms. BUG=None TEST=Examine boot times. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-17mb/google/marasov: Skip MBP HOB creation to save boot timeSubrata Banik
This change skips the MBP HOB creation since coreboot doesn't use it and also helps to reduce the boot time by ~10msec. Boot time data: Before: * 955:returning from FspSiliconInit 897,278 (33,603) After: * 955:returning from FspSiliconInit 864,543 (21,273) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia97cca560869fcfd55e65c2e1719cceec6f3ab7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71873 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-16soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file and use this definition in the mainboard code, so port this back to Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-15mb/google/skyrim/var/winterhold: Update USB port A0 settingEricKY Cheng
Update USB port Type-A Port A0 setting. BUG=b:261650602 TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command. Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-01-15mb/google/brya/var/marasov: Update Aux settingsFrank Chu
Follow hardware design to correct aux setting on USB-C ports to fix DP monitor can not output data through type-C port 0 USB-C port 0 did not have retimer. USB-C port 1 have retimer. USB-C port 0 AUX_DC_P connect to GPP_E22. USB-C port 0 AUX_DC_N connect to GPP_E23. BUG=b:263212450 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage DP monitor display normally Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15mb/google/skyrim/var/winterhold: Update I2C bus0 settingsDtrain Hsu
Update settings for touchpad I2C frequency and data hold time. I2C frequency and data hold time need to meet touchpad spec. - I2C frequency: 380kHz - 400kHz - Data hold time: 0.3us - 0.9us BUG=b:262320419 TEST=On winterhold, touchpad i2c measurement from vendor, Frequencies: 395 kHz, Data hold time: 0.66 us Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-13mb/google/skyrim: remove morthal variantMartin Roth
Morthal has been overcome by events. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-13mb/google/brya/var/omnigul: Update GPIO settingsjamie_chen
Configure GPIOs based from EE. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I5cfaa8fce6df7f09b744fb3e0b7b1d5b6acdc79b Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-12mb/google/skyrim/var/markarth: Update devicetree settingJohn Su
Update devicetree based on the schematic_20230105. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-12mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
2023-01-11mb/google/brya: Enable eNEM support for Tanik and SkolasSubrata Banik
TEST=Able to build and boot Google/Tanik and Skolas to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a21122dbc324d3a396e8934e21d42f471cdb0bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11mb/google/geralt: Use BOE_TV110C9M_LL0 as default mipi panelBo-Chen Chen
We will use BOE_TV110C9M_LL0 for geralt proto board, so update the panel setting. BUG=none TEST=emerge-geralt coreboot; see panel-BOE_TV110C9M_LL0 in coreboot.rom Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I28e9dd87350b55fdc609dd2c562c5a2ad578187c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71786 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/geralt: Keep booting even if MIPI panel not foundBo-Chen Chen
We should keep booting even failed to get the MIPI panel. BUG=none TEST=emerge-geralt coreboot; Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I39d9e04e5908f669ae2a1a8ce8858b93cae20654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71785 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 389 kHz Change-Id: Ie9efd4e597e2701c98064185e5b39a6e256a5f1c Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71772 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-01-11mb/google/nissa/var/craask: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:263920313 TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned fw_config and fw_config set correctly. Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/nissa/var/yaviks: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:251055188 TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned fw_config and fw_config set correctly. On UFS SKU with fw_config set, eMMC no longer shows up in lspci. (On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan so there's no change in behaviour.) Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/brya/var/omnigul: Add memory parts supportAmanda Huang
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) Samsung K3KL8L80CM-MGCT 2) Hynix H58G56BK7BX068 3) Micron MT62F1G32D2DS-026 WT:B 4) Micron MT62F512M32D2DR-031 WT:B BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I699070596a77c975254660a1ba74b0f40026186d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-10mb/google/dedede/var/dibbi: Generate SPD ID for supported partsLiam Flaherty
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:260934724, b:255447299 BRANCH=dedede TEST=build Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71710 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/google/brya/var/marasov: Update DPTF parametersFrank Chu
Add the first version DPTF parameters. BUG=b:264217345 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71634 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang
When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/google/brya: Allow respective variant to choose NEM configSubrata Banik
This patch introduces a new config named `DEFAULT_ADL_NEM` and allows respective brya variants with Alder Lake ESx samples to choose NEM over eNEM as eNEM was fuse disabled till ESx. TEST=The boot flow related to eNEM and NEM behaviour remains the same with and without this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10mb/google/brya/var/marasov: Disable touch panel power for non-touch skuFrank Chu
Disable touch panel power for non-touch sku by fw_config TOUCH field. BUG=b:263452842 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I4736f94481512806377b733b26fdc7290046c555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71691 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09mb/google/dedede: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple dedede variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I212533ffdfb05f841e722c130b52c2976272e670 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on dedede variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). Since the fast majority of dedede variants have a touchscreen option, and those that do use the same GPIOs for enable/reset, set the GPIOs for touchscreen operation in the baseboard and then override for the few (3) variants that do not have a touchscreen. BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ic216827a4b53d1d35913efca63a43d4672791c54 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/brya: Increase Resizable BAR address space limit to 33 bitsTarun Tuli
The dGPU used for some Brya projects requests 33 bits of address space for one of its BARs via the Resizable BAR mechanism (requires 6GB). This Kconfig is currently set at 32 bits for brya, so the allocation currently is capped at 32 bits (4GB). This patch sets the limit to 33 bits for brya boards, which is enough for the GPU. BUG=b:214443809 TEST=all of the dGPU PCI BARs on agah can be successfully allocated Change-Id: Ia791be5108fb07a256ae62fc2aee2f057909ef12 Signed-off-by: Tarun Tuli <tarun@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-09mb/google/brya/var/lisbon: Update RTL8168 LAN LED configRobert Chen
Adjust LAN LED config to 0x060f. BUG=b:246657849 TEST=emerge-brask coreboot Change-Id: Idd5ed2bf7eb4ee5990f2a842cba43f967ae3825e Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71698 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09mb/google/brya/var/gladios: Update RTL8168 LAN LED configRobert Chen
Adjust LAN LED config to 0x060f. BUG=b:239513596 TEST=emerge-brask coreboot Change-Id: I17b844b89569fb7653454fd08782fc961c715817 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71697 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09mb/google/skyrim/var/markarth: Enable DPTC supportJohn Su
Enable DPTC support for markarth. BUG=b:263216451 TEST=emerge-skyrim coreboot Change-Id: I18c2c840037f65f4f2ca92054247cece28843e45 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71720 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/nissa/var/xivu: Update DPTF parametersIan Feng
Follow thermal table from thermal team. 1. Enable TS3 thermal sensor. 2. Set TS3 passive policy to 63. 3. Set TS3 critical policy to 73. 4. Modify TSR2 passive policy to CPU. BUG=b:263554342 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ia1fcaee15a8b58b755ce0a48a1978e795b66efd7 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71658 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernetRobert Chen
Add ACPI DmaProperty for gladios. BUG=b:239513596 TEST=Verified SSDT on gladios unit. Before: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) } } After: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } } Change-Id: I1c4f6ff7b3eda114f4f365a963c089fe584d8aee Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71699 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-08mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstageMartin Roth
Because skyrim is loading ramstage from SPI with the DMA engine, the size of the compressed image is less important to load speed than decompression time. Because the LZ4 decompression is so much faster than LZMA, compressing with LZ4 saves us roughly 30ms in boot time. For size, we're spending roughly 57KiB: fallback/ramstage 0x9b00 stage 130864 LZMA (305316 decompressed) fallback/ramstage 0x9b00 stage 189126 LZ4 (305316 decompressed) Right now we have 2MiB empty space in Skyrim's RO before this change, and roughly 550KiB empty space in RW, so there aren't currently any size worries. Just for fun, I also tested uncompressed ramstage, and it was still 18ms faster than LZMA, but that makes it roughly 12ms slower than LZ4. BUG=b:264409477 TEST=Boot skyrim, look at boot speed. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-08mb/google/dedede: Create dibbi variantLiam Flaherty
Create the dibbi variant of the waddledee reference board by copying the template files to a new directory. BUG=b:260934018 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a includes GOOGLE_DIBBI Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286 Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71709 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B. Add new ram_id:0010 for Micron MT62F512M32D2DR-031 WT:B The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-08mb/google/nissa: Enable eNEMReka Norman
Enable eNEM for all nissa variants. This is mostly done to be consistent with other recent Intel platforms. It's not strictly necessary since on nissa the LLC size is larger than the total code + data size used in CAR. There is no change in boot time. BUG=None TEST=Boot to OS on craask Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08mb/google/nissa/var/craask: remove SAR UNUSED fw_configEric Lai
This bit is dropped in factory. All skus can use table ID_0. BUG=b:251287101 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71690 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFCDavid Wu
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, it will treat missing SSFC as zero, so Kano needs to set the ov2740 to 0 to avoid probing wrong mipi camera. Before patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556 >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT After patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >I2C: 00:20 disabled by fw_config >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT BUG=b:262939431 TEST=Boot on kano and check functional with ov2740 camera. Change-Id: I46fac6c820d6006956680a07198db82225630905 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-07mb/google/rex: Disable stage cacheSubrata Banik
This patch disables the stage cache to save boot time. Note: S3 is not POR for Intel MTL mobile skus. Boot time is reduced by ~8ms. Boot time before: 4:end of romstage 1,391,225 (13,724) 100:start of postcar 1,403,339 (12,114) Boot time after: 4:end of romstage 1,380,262 (5,618) 100:start of postcar 1,392,323 (12,060) Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-06mb/google/brya/var/omnigul: use i2c1 for TPMjamie_chen
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the omnigul variant. BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-06mb/google/brya/var/omnigul: use RPL FSP headersjamie_chen
To support an RPL SKU on omnigul, omnigul must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL FSP headers for omnigul. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85 Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71702 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06mb/google/nissa/var/craask: Modify GPIOs for NVMeRen Kuo
Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:259211172 TEST=Verify on reworked craask DUT to boot up from NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71170 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06mb/google/nissa: Disable stage cacheReka Norman
Although S3 is supported on nissa, only S0ix is used on user devices, so we can ignore optimising the S3 resume time. Disable the stage cache to save boot time at the cost on increasing the S3 resume time. Boot time is reduced by ~6 ms. This is mostly from adding postcar to the stage cache, which is slow since TSEG is not cached in romstage. Adding ramstage and FSP-S take negligible time. The S3 resume time is increased by ~89 ms total from loading and decompressing ramstage and FSP-S. Boot time before: 3:after RAM initialization 573,295 (931) 4:end of romstage 583,569 (10,274) 100:start of postcar 587,729 (4,160) Boot time after: 3:after RAM initialization 571,527 (830) 4:end of romstage 575,712 (4,185) 100:start of postcar 579,866 (4,153) S3 resume time before: 101:end of postcar 368,904 (0) 10:start of ramstage 369,165 (260) 971:loading FSP-S 385,742 (16,577) 30:device enumeration 407,105 (21,362) S3 resume time after: 101:end of postcar 363,101 (0) 8:starting to load ramstage 363,101 (0) 15:starting LZMA decompress (ignore for x86) 382,802 (19,701) 16:finished LZMA decompress (ignore for x86) 431,620 (48,817) 9:finished loading ramstage 431,850 (230) 10:start of ramstage 431,927 (76) 971:loading FSP-S 448,357 (16,430) 17:starting LZ4 decompress (ignore for x86) 474,420 (26,062) 18:finished LZ4 decompress (ignore for x86) 474,627 (206) BUG=b:247940538, b:192032803 TEST=Boot and S3 suspend/resume on craask Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-05mb/google/skyrim/var/markarth: Update GPIO settingsJohn Su
Configure GPIOs based on b/263534907#comment4 from EE. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71635 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-05mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterunChris.Wang
Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05mb/google/brya/var/marasov: Disable FPMCU interfaceFrank Chu
Set fingerprint control GPIO to NC by HW design. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71650 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 23:29:08 +0000