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2018-01-25mb/google/poppy/variants/nami: Disable SATAKane Chen
This change disables SATA controller in order to make SATA IP enter low power status. BUG=b:72332817 TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status and verify SATA IP enters low power state Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23354 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25mainboard/google/zoombini: add ACPI entry for cr50Caveh Jalali
This adds coreboot device tree entries on zoombini & meowth for the cr50. Also, fixes the GPIO pin IRQ settings to be falling edge. This is based on what we do for fizz. BUG=b:71722449 TEST=booted to linux on meowth: tpm_version command now sees the cr50. localhost ~ # tpm_version TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 localhost ~ # uname -a Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux localhost ~ # and we see interrupts when talking to the cr50: localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru pts 84: 4687 IO-APIC 84-edge cr50_spi TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 84: 4799 IO-APIC 84-edge cr50_spi localhost ~ # Change-Id: I9d503334502503ef49515e4a8736d967bc454a98 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-25mb/google/poppy/variants/nami: Enable elan touchpad wakeup system from S3/S0ixVan Chen
BUG=b:71839089 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. powerd_dbus_suspend 3. touch touchpad to wakeup system 4. localhost ~ # cat /var/log/eventlog.txt | 2018-01-21 17:01:59 | S0ix Enter | 2018-01-21 17:02:04 | S0ix Exit | 2018-01-21 17:02:04 | Wake Source | GPIO | 80 Change-Id: Ie550cfa3f7b5fd105f89c16076d428743392d0e4 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23363 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-24mb/google/fizz: Add AC/DC loadline settingsGaggery Tsai
This patch adds AC and DC loadline settings since vr_config_enable is set. Without correct AD/DC loadline settings, VRs reported incorrect VID values which caused CPU freqency clipping. The clipping reason could be retrieved from MSR 0x64F. From VRTT report, the AC/DC loadline resistances are within spec, we can use default value defined in Table 6-1, doc #543977. BUG=b:70646304 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline settings from DCI to ensure the values were programmed correctly. Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23349 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23mainboard/google/fizz: Tune audio i2c parametersShelley Chen
Tune I2C params for I2C bus 5 to ensure that the frequency does not exceed 400KHz. BUG=b:65058277 BRANCH=None TEST=Measured bus frequency for audio <= 400MHz Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23grunt: Enable TPMChris Ching
Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create the appropriate selection based on selected board, and if grunt then define the I2C address. BUG=b:69416132 BRANCH=none TEST=make all Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22960 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mb/google/reef,sand: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-23google/kahlee/BiosCallOuts.c: Remove platform_FchParams_resetRichard Spiegel
Function platform_FchParams_reset() is now an empty function, remove it, its header declaration and its use. BUG=b:64140392 TEST=Build kahlee. Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO tableRichard Spiegel
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data from agesa_board_gpios[], wrap format and delete agesa_board_gpios[] and get_gpio_table(). Then remove the get_gpio_table() call from BiosCallOuts.c. Finally, remove get_gpio_table() from google/kahlee/variants/baseboard/include/baseboard/variants.h. BUG=b:64140392 TEST=Build grunt. Build and boot kahlee, recording serial output. Search for "stage bootblock" and "stage ramstage", indicating GPIO being programmed. Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23soc/amd/stoneyridge/southbridge.c: Create a GPIO programming functionRichard Spiegel
Create a GPIO programming function that can be called from multiple stages (bootblock, romstage and ramstage) that will program only the GPIO specific to the particular stage. Add dummy table to kahlee, grunt and gardenia to be able to test a build. BUG=b:64140392 TEST=Build kahlee, grunt and gardenia with GPIO programming call at bootblock. This call is removed before commit, so bootblock.c is not committed. Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23mb/google/poppy/variants/nami: Remove iccmax setting from devicetreeFurquan Shaikh
Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings) provides correct iccmax settings for kbl-u based on the SKU. Thus, there is no need to override these values in devicetree. This change gets rid of iccmax settings in the nami devicetree. Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-22mainboard/google/zoombini: mrc cacheCaveh Jalali
this enables the MRC recovery cache for zoombini & variants. the Kconfig options are: HAS_RECOVERY_MRC_CACHE MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN one note of caution: early board builds will likely fail to boot with: tlcl_extend: response is 0 tlcl_extend: response is 0 tlcl_lock_nv_write: response is 0 tlcl_lock_nv_write: response is 28b Failed to lock rec hash space(1f) Saving nvdata hard_reset() called! the fix is to boot into recovery once, then it's business as usual. using servo, this can be done with: dut-control power_state:rec BUG=b:71785303 BRANCH=chromeos-2016.05 TEST=boots on meowth... Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23298 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22mainboard/google/zoombini: add EC to ACPI tablesCaveh Jalali
this adds missing ACPI entries for the EC, CPU, and power button. also, the EC to AP wakeup pin assignment is fixed. BUG=b:71819257 BRANCH=chromeos-2016.05 TEST=booted on meowth. /sys/class/power_supply now gets populated. Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/23237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-01-22mb/google/fizz: Remove IccMax settings from DTGaggery Tsai
This patch removes IccMax settings from device tree since they are handled in SoC code from patch e1a75d. BUG=b:71369428 BRANCH=None TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure the IccMax settings passed to FSP are from SoC code. Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: enable PCH_FP_PWR_ENVincent Palatin
Turn on the load switch to the FP MCU at startup, so the kernel can detect it and use it. The load switch enable pin is connected to the GPP_A11 PCH pin (aka PCH_FP_PWR_EN). BRANCH=none BUG=b:71986991 TEST=on Meowth, see the kernel detecting a cros_fp device at startup: [ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected. [ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: configure FP MCU SPI deviceVincent Palatin
Configure the FP MCU interface on GSPI1. BRANCH=none BUG=b:71986991 TEST=boot on reworked Meowth with a ZerbleBarn board attached to GSPI1 and see the cros_ec kernel driver detecting it. Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-18mainboard/google/zoombini/variant/meowth: add memory optionsNick Vaccaro
Add support for new memory stuffing options that will appear on the P1 meowth boards. new strap setting - associated SPD file ---------------------------------------- 0b001 - Hynix_H9HCNNN8KUMLHR_1GB.spd.hex 0b010 - Samsung_K4F6E3S4HM_2GB.spd.hex 0b011 - Hynix_H9HCNNNCPUMLHR_4GB.spd.hex BUG=b:69011806 BRANCH=none TEST=none Change-Id: Ief07f3de351d01cbc195b785c36e96de0cbf7ddb Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17google/fizz: Fix barrel jack values for U42 and U22Shelley Chen
Our current U22 skus (celeron and i3) actually don't support PL2, but making sure that if we do decide in the future to use it to make sure PL2 and PsysPl2 values are set appropriately. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42 and 65W with barrel jack for U22. Change-Id: I084d0320128a6e05948023520a30c497c41be23b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17mb/google/poppy: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17mb/google/nautilus: Add MIPI camera asl files for IMX258 and DW9807Andy Yeh
* Add IMX258 sensor entity * Add DW9807 VCM control entity * Enable CIO2 and IMGu in devicetree.cb TEST: Verified the MIPI camera function on DUT board Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Move PMIC specific objects to appropriate scopeRizwan Qureshi
Right now the poppy baseboard camera topology allows to add maximum of 2 sensors. The sensors can be of different vendors. The current ASL code structure doesn't allow sensor customization. Moving PMIC specific objects from sensor objects to PMIC scope and having separate sensor ASL files will help in unbinding the PMIC and sensor objects and allow some customizations. BUG=None BRANCH=None TEST=Build and boot soraka, make sure both camera's are working fine and also verify that the generated DSDT looks fine. Change-Id: I63ae1a685b78bda212c5c48a4c2dc744164a3cb5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Split ports and endpoints config for CIO2Rizwan Qureshi
The variant boards can have a custom endpoints, splitting the ASL code aids customizing the endpoints as per the variant board setup. BUG=None BRANCH=None TEST=build boot soraka, verify that the cameras are working fine and generated DSDT tables are same as before. Change-Id: I5f1cded25bfb6a7baf18b211f9773dfecdc2f264 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-15mb/google/poppy/variants/nami: Enable elan touchpadvan_chen
BUG=b:71838954 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: Elan Touchpad Change-Id: I14471d1473a3b3ecf15aaf362b47874704cd3bf0 Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-13mainboard/google/kahlee: Finish GPIO90 setup for GruntMartin Roth
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly, but these additional registers need to be set to use it as a GPIO. - Split structures into variant specific versions. These will be moved into the variant tree in a follow-on patch - Set GENINT_DISABLE bit - Disable interrupts for this GPIO. BUG=b:71867096 TEST=Build and boot grunt. Verify registers are set correctly. Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23228 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13mainboard/google/kahlee: Fix GPIO tableMartin Roth
The GPIOs that are being set low had the wrong value getting set. FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE. BUG=b:70234300 TEST=Build and boot Grunt Change-Id: I16792b76252506a43aac92738b04096ae3fde01c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-13google/kahlee/grunt: Add grunt touchpad ASLDaniel Kurtz
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD, respectively. Since grunt is the 'baseboard', put its configuration under baseboard, and include it from the grunt variant. BUG=b:71820409 TEST=Boot grunt to kernel, use evtest to test trackpad. TEST=Boot kahlee to kernel, use evtest to test trackpad. Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23232 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13google/kahlee/grunt: Add Grunt audio codec ASLDaniel Kurtz
Grunt and Kahlee have different audio codecs. Create a new audio .asl for the baseboard for grunt's codec, link to it from the grunt mainboard, and move the kahlee codec table from the baseboard mainboard to its own .asl in variant/kahlee. Note, we can't use the generic drivers due to the PCI scope expectation. The AMD I2C are not PCI devices. BUG=b:69397774 TEST=Codec driver loads. Check dmesg. Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23226 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13google/kahlee/grunt: Move ASL to variantsMarc Jones
Move the apci/ to the baseboard and move mainboard.asl to each variant. BUG=b:71873651 TEST=build BRANCH=none Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23229 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-13mainboard/google/zoombini/variants/meowth: set GPD_2 to NF1Nick Vaccaro
Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must be set to use NF1 instead of gpio. BUG=b:64395641 BRANCH=none TEST=none Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/google/poppy/variants/nami: Fix DA7219 IRQ issueKaiyen Chang
Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to meet the requirement of DA7219 IRQ pin. BUG=b:70646770 BRANCH=none TEST=Use aplay and arecord to verify headphone function. Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23160 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-12mb/google/fizz: update DPTF settingsKevin Chiu
TCPU: _CRT: 100 _PSV: 93 _TRT: 100/5(s) TSR0: _CRT: 83 _PSV: 70 _TRT: 100/10(s) TSR1: _CRT: 73 _PSV: 67 _TRT: 100/30(s) TCC: 6 for 94'C PL1: max: 15W min: 3W BUG=b:70294260 BRANCH=master TEST=build Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mb/google/fizz: Disable PCH LanKane Chen
Fizz has external Lan on PCIE port. The Lan device on PCH is not used. BUG=b:70889517 Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/google/poppy: Remove digitizer reset control from ACPIFurquan Shaikh
Digitizer power is not controlled by SoC. Also, since the digitizer uses I2C-HID driver in Linux kernel, the device is put into sleep anytime system is suspended. Thus, there is no need to control the reset gpio using ACPI power resource. TEST=Verified that digitizer device is properly detected on boot-up and after suspend/resume. Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/google/poppy/variants/nautilus: enable digitizer pen deviceSeunghwan Kim
- Add pen device property into devicetree.cb. - Set GPP_C9 to 0 as default. BUG=none BRANCH=master TEST=emerge-nautilus coreboot and check pen device operation Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f Reviewed-on: https://review.coreboot.org/23010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mainboard/google/kahlee: Enable PCIe Lane 2Martin Roth
The Port initializer had been changed from PortDisabled to PortEnabled, but engine inializer hadn't been updated from PcieUnusedEngine to PciePortEngine. Update this so the port works. Also change disabled port to PcieUnusedEngine. BUG=b:71818026 TEST=PCIe device now shows up on D2F4 Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23210 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-11google/fizz: Dynamically set PsysPl2 MSR if using type-C chargerShelley Chen
If using type-C charger, then PsysPl2 may be lower than barrel jack value of 90W, so need to override value to the max power of type-C charger. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 60W with zinger, but 90W when using proper barrel jack adapter on and i7. Change-Id: If955b9af0e23f47719f001f1d73ec37113937cea Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: map EC io space in devicetree.cbNick Vaccaro
BUG=b:64395641 BRANCH=none TEST=none Change-Id: I92969384cd32766be4595494aa70b4eb9c74f099 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: add gpio init to ramstageNick Vaccaro
-add initialization of gpio table to mainboard_silicon_init_params() -fix input parameter type for mainboard_silicon_init_params() for FSP2_0. BUG=b:69011806 BRANCH=chromeos-2016.05 TEST=none Change-Id: If8cba786a127a8704eb240380841362e3eb06552 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini/variants/meowth: map EC io spaceNick Vaccaro
Map EC io space in devicetree.cb BUG=b:69011806 BRANCH=none TEST=none Change-Id: Ic3806b5f9b7bf272a77360060cd71db9a03d5763 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini/variants/meowth: Disable EC SW syncNick Vaccaro
BUG=b:69011806 BRANCH=chromeos-2016.05 TEST=Compiles successfully using "./util/abuild/abuild -p none -t google/zoombini -x -a" Change-Id: I8276fa26af664557e9964cb6b8a5a076eacdf00c Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: add ec.c and ramstage.c to buildNick Vaccaro
-add ec.c to bootblock if CONFIG_EC_GOOGLE_CHROMEEC -add ramstage.c to ramstage. BUG=b:69011806 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' compiles correctly. Change-Id: I7ec1e22339f3e4d9a8d83093bcc2ce725c9c99e7 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini/variants/meowth: fix gpio settingsNick Vaccaro
-change GPP_C12 (H1 IRQ) to use GPI_SCI_LOW and level triggered -set gspi gpios to no connects if CONFIG_ZOOMBINI_USE_SPI_TPM not set BUG=b:69011806 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' succeeds Change-Id: Ida1d1050db12982c3c497656162cc84c62a77f70 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: enable USB and assign acpi irqNick Vaccaro
-add USB2 and USB3 to devicetree -add TPM_TIS_ACPI_INTERRUPT to Kconfig -map gpe0_dw0, gpe0_dw1, and gpe0_dw2 blocks BUG=b:64395641 BRANCH=chromeos-2016.05 TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: fix spd makefilesNick Vaccaro
The spd.bin file was not getting generated properly, so moved logic to variant's makefile. BUG=b:64395641 BRANCH=none TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully and spd.bin is found when booting. Change-Id: I4642d6ddb5e65f721d1bde31ca0ca5b4438da554 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-10mainboard/google/kahlee: Update SPD MakefileMartin Roth
The .spd.hex text is added to the name by the build process. This was causing a failure because we were trying to add the files: 'file.spd.hex.spd.hex' to the build. Remove the additional .spd.hex text. BUG=b:71535311 TEST=Build Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-01-09mb/google/fizz: Turn off SATA SALPKevin Chiu
turn off SATA SALP to prevent 0x5A/0x5B error on Sandisk SSD in below conditions: 1. reboot stress 2. FAFT BIOS qualification BUG=b:70146894,b:69984821,b:70590720 BRANCH=master TEST=pass firmware_ConsecutiveBoot 2500 loops FAFT BIOS test pass Change-Id: I5d57dd8ef256d5f0a1027ab77f63da62c6c9ce74 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-09mainboard/google/zoombini/variants/meowth: add new boardNick Vaccaro
Add Meowth board, which derives from Zoombini, a CNL reference board. BUG=b:69011806 BRANCH=master TEST=Compiles successfully using "./util/abuild/abuild -p none -t google/zoombini -x -a" and boots Meowth. CQ-DEPEND=CL:22908 Change-Id: Ie6ed7ebb4a00a87fc93fc694d74c08a716380a54 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-09mainboard/google/zoombini: Provide memory configuration variant APINick Vaccaro
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-09mb/google/poppy: Add internal pull-up on pen eject signalFurquan Shaikh
Since the current hardware revision does not have external pull on the pen eject signal, this change adds internal pull-up on it. Change-Id: I426d9833d7efbd8735b6f2b4896d1012b62cb4b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-08google/gru: switch to spi2 for all scarlet based boardsEge Mihmanli
Rainier, a scarlet derived board, was configured to use spi0 for tpm driver by default. This patch switches it to spi2 to reflect recent changes in scarlet-derived boards. Change-Id: Ib67109786512c068bb957890f456bccff7addc86 Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/23129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05mainboard/google/zoombini: Add SoC acpi files to dsdt.aslNick Vaccaro
BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-05mainboard/google/zoombini: Fix some devicetree pci settingsNick Vaccaro
- Enable I2C #2, #3, and #5 - Enable UART #2 - Enable GSPI #0 and #1 - Disable SATA - Set pci 1f.0 to chromeec BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-05mainboard/google/zoombini: add mainboard_opsNick Vaccaro
Add mainboard.c to ramstage. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ic7275b07f28a99a91b978d2e8c4118c6858705bc Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-05mainboard/google/kahlee: Update Grunt devicetree.Justin TerAvest
Grunt's devicetree dropped some entries when it was split from the kahlee variant. This commit restores: spd_addr_lookup - memory information for AGESA dram_clear_on_reset - keeps DRAM contents on reset uma_mode - needed for vbios uma_size - needed for vbios Change-Id: I1d8cdc97594867f1d706318370055087976a5104 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02mb/google/poppy/variants/nami: Add empty_ddr4.spd.hex for DDR4Kane Chen
The spd size of DDR4 is 512, but the size empty.spd.hex is 256. With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data loads spd data incorrectly due to the offset is wrong. Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-02google/fizz: Enable SataPwrOptEnable FSP UPDKane Chen
This change is to enable SataPwrOptEnable. With this change, we no longer see SError message in kernel during suspend_stress_test. BUG=b:70491485 Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22mb/google/fizz: revise LED0 behavior for link speed 100MbGaggery Tsai
This patch revises LED0 Green light behavior from patch 2ecf3f8c. For 100Mb link speed, LED0 should be OFF. BUG=b:65437780, b:68284778, b:69950854, b:65808944 BRANCH=None TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe LED0 is behaving as expected. Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22964 Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-21google/fizz: Enable ec sw sync gbb by defaultShelley Chen
firmware test team is requesting that default gbb flags set to 0x39 rather than 0x239 so that it's consistent with the default gbb flags of other platforms. BUG=b:70392534 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage gbb_utility --get --flags image-fizz.bin and make sure that it returns 0x39 instead of 0x239 Change-Id: Ib73e4619b13f6b7c2d01598c926fbbd7d7eb9bef Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22962 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-21mainboard/google/fizz: Enable S0ixShelley Chen
Enable S0ix for fizz. BUG=b:67598361 BRANCH=None TEST=None. Need to be tested with EC and kernel as well. Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22955 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-21google/kahlee: Select fanless SMU firmwareMarshall Dawson
Don't rely on the cascading default values. Ensure Kahlee uses the fanless versions of the SMU fimware by selecting it. Change-Id: I0761266f2a4026ebc251b64074c10481118734a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20mb/google/fizz: Enable mbox command for ISL VR c-state issueRizwan Qureshi
There is a potential IMVP8 issue for KBL that affects Intersil VRs Fizz is using one of the affected parts. The fix is to use an updated microcode and also send a mailbox box command from FSP. BUG=b:65499724 BRANCH=None TEST=Build and boot Fizz Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/22763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/google/poppy/variants/nautilus: Change USB2 phy settingsh.kim
In order to pass USB2 eye diagram, some USB2 port PHY registers needs to be changed. Port1 (Type-A): USB2_PORT_SHORT Port2 (BT): USB2_PORT_SHORT Port6 (H1): USB2_PORT_SHORT Port7 (Camera): USB2_PORT_SHORT BUG=none BRANCH=master TEST=emerge-nautilus coreboot and do eye-diagram test Signed-off-by: sh.kim <sh_.kim@samsung.com> Change-Id: I174e5bf96a53bb210481fb88298d5341f6c11dec Reviewed-on: https://review.coreboot.org/22686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20intel/bd82x6x: Use generated ACPI PIRQTobias Diedrich
Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 (sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X. This generates the main ACPI _PRT table automatically based on the chipset registers. Tested on Intel NUC DCP847SKE with Linux 4.13.14: $ cat /proc/interrupts CPU0 CPU1 0: 23 0 IO-APIC 2-edge timer 8: 1 0 IO-APIC 8-edge rtc0 9: 0 0 IO-APIC 9-fasteoi acpi 19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1 23: 0 0 IO-APIC 23-fasteoi i801_smbus [...MSI and other interrupts skipped...] Log messages: ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6 ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4 ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4 ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8 ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1 Generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20google/gru: Adjust to incorrect strapping resistors on KevinJulius Werner
It seems that RAM code 0 has been strapped with an incorrect resistor on Kevin. The resulting voltage divide still puts it well within the ADC value bucket reserved for that slot, but a little closer to the edge than necessary. While this doesn't seem to cause any immediate problems on its own, it still doesn't hurt to fix it (if only for the documentation value). On other boards (at least on my Scarlet) the strapping seems to be correct. Change-Id: Ic5199834fbeaf734e725ff45b04f45eefe149855 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22891 Reviewed-by: David Schneider <dnschneid@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-20google/gru: Prettify strapping ID ADC tableJulius Werner
This patch shifts some comments around to make it easier to replace values in the ADC strapping bucket table with compile-time conditionals. Change-Id: Ic51917d3961a51d4e725ff824fb59aeefe149855 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-20mb/google/poppy/variants/nami: Add SPD files for namiFurquan Shaikh
This change adds SPD files for memory IDs 1-4 on nami. BUG=b:70182907 Change-Id: Ic43f944c0cde18244fe4c4d21314b831d048a3a2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20mb/google/poppy: Enable speaker and codec for namiGaggery Tsai
Nami uses MAX98357A speaker amplifier and DA7219 codec. This patch adds max98357a and da7219 under I2C #3 in devicetree and adds SPK DMIC nhlt support for 4CH DMIC. BUG=b:70646770 TEST=emerge-nami coreboot Change-Id: Iecf4059f8ea3d5e34f33f0be227897a8cca636fa Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-19mb/google/poppy: Configure WWAN gpiosFurquan Shaikh
BUG=b:70773281 Change-Id: If9b575568cabcbee03ad190b69d9c033890f7fa6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22927 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure GPP_B0 for WLAN wakeFurquan Shaikh
As per the latest schematics, this change configures GPP_B0 for WLAN wake and uses corresponding gpe bit in ACPI node for WLAN. This hasn't been tested yet. BUG=b:70775494 Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22928 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure pen reset and eject linesFurquan Shaikh
This change configures the GPIOs for pen reset and eject lines and exports required properties using ACPI table. BUG=b:70773138 Change-Id: I52f6c3dced54259cde8ee6753275622622e15954 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 1Furquan Shaikh
Similar to other KBL projects, this change enables AER and LTR for root port 1 on poppy. BUG=b:65570878 Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_B8 for WLAN_PE_RSTFurquan Shaikh
BUG=b:62726961 Change-Id: I5a88e67d5a22f8a39427c95821ffee4f2fd717fa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nami: Fix SATA configs againFurquan Shaikh
This change really fixes the SataMode to select non-RAID mode and enables SATA which was incorrectly disabled in a71276b (mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree). BUG=b:70160119 Change-Id: Ied6adabdc1d2458972bde628616a198cd41f9f3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_F3 as NCFurquan Shaikh
GPP_F3 is not connected on poppy or any of its variants. This change configures GPP_F3 as NC on poppy and all the variants. BUG=b:70160119 Change-Id: I303276ab9546d56c846755fa3a6142978f6b8c92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nami: Fix GPIO configuration for DEVSLPFurquan Shaikh
Nami uses DEVSLP1 and not DEVSLP0. This change updates the GPIO configuration for DEVSLP to match the latest version of schematics. BUG=b:70160119 Change-Id: Ifa181322011a4b8947ecd0fa44dcf790b0d8f657 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/fizz: Enable 2nd NIC ledsDavid Wu
This patch enables customized NIC leds as below: Green Orange (Amber) 100M off blinking 1000M on blinking BUG=b:69950854 TEST=Boot on fizz dut and observe the LEDs are behaving as expected. Perform suspend/resume test and the LEDs are still working as expected. Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/22817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-17mb/google/poppy/variants/nami: Fix SataMode configuration in devicetreeFurquan Shaikh
Similar to Fizz, SataMode on nami should be set to AHCI. This change fixes the configuration error done in 903472c (mb/google/poppy/variants/nami: Add support for nami board). BUG=b:70160119 Change-Id: Ia88b56ae6bd9121f8447f7c1a2f5a10990fb8ed5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22845 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-17mb/google/poppy/variants/nami: Fix GPIO config for PCH_SPK_ENFurquan Shaikh
PCH_SPK_EN uses GPP_A23 and not GPP_A22. This change fixes the gpio configuration error in the initial change 903472c (mb/google/poppy/variants/nami: Add support for nami board). BUG=b:70160119 Change-Id: I90d9c009369c53cfec47fe77356e181d5ecf7ad5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22844 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-15mb/google/snappy: add reset pin for Melfas touch controllerKevin Chiu
Melfas kernel TS driver (melfas_mip4.c) will look up "ce" GPIO during driver probe in ACPI _DSD. But FW does not report "ce-gpios" but "enable-gpios" in _DSD. Kernel will obtain GPIO from _CRS by index "0" without ID. Melfas driver does not have separate condition for MIT-410 so driver will set TS IC power off in probe. FW now may need to add back "reset" pin in order to hack this condition to let Melfas driver get "useless" GPIO so TS IC power (VTSP) will be not off during driver probe by itself. BUG=b:70149336 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: Icf0451ff0c3df97cb2474e30542a2f46ba67d82a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/22858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-15mb/google/fizz: set SataMode to AHCI modeKane Chen
For Fizz, the default should be AHCI mode and not RAID mode. Additionally, there is only one drive connector, so attaching several drives for a RAID is hard. BUG=b:70146894 Change-Id: I2a9aa2d6281a916c00ff4659a927f164ba0e0705 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22837 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-14mainboard/google/kahlee: Update overcurrent pinsMartin Roth
The overcurrent pins on kahlee weren't mapped correctly, causing the USB-A port to stop working. None of the EHCI only ports are used for external connectors, so all of the overcurrent pins should go to the XHCI connections. This is also true of the Grunt board. On Grunt, this also means that we don't need OC3, as it doesn't map to anything in the XHCI controller, as it's coming from an internal hub. BUG=b:70636233 TEST=Build & boot Kahlee, verify USB-A port is working again. Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2017-12-13mb/google/poppy/variants/nami: Disable native SD card controllerFurquan Shaikh
This change selects Kconfig option to disable native SD card controller in ACPI tables, since it is not used on nami. BUG=b:70160119 Change-Id: I6180c2b342c69e6a7c357f10b6297d67ea0211d7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13mb/google/fizz: Enable SATA on port 0David Wu
Enable SATA port 0 to support SATA HDD. BUG=b:69950854 BRANCH=None TEST=emerge-fizz coreboot and boot on fizz dut Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/22815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-12google/kahlee/grunt: Add SPD filesMarc Jones
MEM_ID SPD 0000 hynix-H5AN8G6NAFR-UHC 0001 hynix-H5ANAG6NAMR-UHC 0010 micron-MT40A51216JY-083E 0011 micron-MT40A1G16KNR-075E 0100 samsung-K4A8G165WB-BCRC 0101 samsung-K4AAG165WB-MCRC BUG=b:69268926 TEST=build test Change-Id: I1fd6335b3f8842252c42009a0a91a5b6ed3ea238 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12google/scarlet: support INNOLUX P097PFG panelLin Huang
Add INNOLUX P097PFG panel timing. According to Scalet schematic, if GPIO3_D4 get low status, it will use INNOLUX P097PFG panel; if GPIO3_D4 get high status, it will use KD097d04 panel. Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-12mb/google/poppy/variants/nami: Implement variant_memory_paramsFurquan Shaikh
This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11mb/google/poppy/variants/soraka: Tune I2C5 paramsFurquan Shaikh
This change updates scl_lcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:65062416 TEST=Verified that I2C5 frequency is between 389-396kHz. Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11soc/amd/common: Move files to common/blockRichard Spiegel
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11google/gru: Stop mucking with unused I2S0 pins in codec configJulius Werner
Due to a schematic error, our code was written to configure more I2S0 pins than are actually used. We're also pinmuxing the whole bank of pins over to the I2S controller even though we don't need them all. Restrict the GPIO initialization and pinmuxing to the pins we really need so the other ones can be correctly used as SKU ID pins on Scarlet. Also, move the "audio" IO voltage domain selection to the other such selections in the bootblock, since that covers two whole banks of GPIOs and there's no guarantee that they're all used for audio (and thus not needed before ramstage). BUG=b:69373077 TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2. Change-Id: I9314617e725fe83d254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-12-11google/gru: Change Scarlet SKU ID pins to pull-upsJulius Werner
These pins need to be pull-ups. I forgot. BUG=b:69373077 Change-Id: I9314617e01d35898254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-11google/nautilus: Add Maxim98357a supportNaveen Manohar
Adds Maxim98357a support for Nautilus using the generic driver in drivers/generic/max98357 BUG=b:68686020 TEST=With entire merged audio should be enabled on max98357 speaker codec. Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11mb/google/poppy/variants/nautilus: add SPK DMIC nhlt supportNaveen Manohar
Nautilus board uses max989357a speaker codec and 4CH DMIC. Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on Speaker and captures on 4CH DMIC Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-09google/cyan: fix FSP memory init paramsMatt DeVillier
In the original Chromium source, PcdMemorySpdPtr is only set for cyan, but none of the other Braswell variants. When upstreamed, it was left set for all boards as it didn't appear to be problematic. In wider testing, I came across one reks board for which it caused FSP memory init to fail, so restricting the parameter to cyan only as it was originally. TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM, observe board now successfully boots where it did not previously. Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22782 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-09mainboard/google/kahlee: Update GPIOsMartin Roth
- The touchscreen interrupt was moved from the GPIO 3, as originally suggested to GPIO 11. This changes the gevent from 2 to 18. - Add EMMC reset on GPIO 93. - Add EMMC bridge PCIe reset on GPIO 40. - Set device enables to high. - Remove extra SCI comment from GPIO 130. - Set individual device PCIe reset pins to high. - Enable global PCIe reset on GPIO 26. - Mark LPC_CLK1 as unused. - Update net names based on latest schematics. - Set Direction and level/edge correctly for SCIs/SMIs. - Remove SCI for pen detect. - Add comments. BUG=b:70234300, b:69681660, b:69305596 TEST=build grunt Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-09mainboard/google/kahlee: Update PCIe port mapMartin Roth
- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on PCIe port 1, so move the OemCustomize file into the variant directory. - Add comments in baseboard version so it's easier to understand. - Update reset pins, put the definitions in gpio.h BUG=b:70255003 TEST=Build and boot Kahlee. Build Grunt. Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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