diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2017-10-18 17:13:07 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-01-18 01:35:31 +0000 |
| commit | 64e2d19082636de9e82674ccfca574269bb34712 (patch) | |
| tree | dfe44c9b1cebbb611b99474c1ee096e23f930796 /src/mainboard/google | |
| parent | 4fef7818ecd002e5971ea6287e402fd9276b7266 (diff) | |
security/tpm: Move tpm TSS and TSPI layer to security section
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/gru/chromeos.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/link/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/oak/tpm_tis.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/parrot/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/stout/romstage.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 38f7f6987e..8d0acbbf2d 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -17,7 +17,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <tpm.h> +#include <security/tpm/tpm.h> #include "board.h" diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 733aa301ef..e23eced50f 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -35,7 +35,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <tpm.h> +#include <security/tpm/tpm.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> diff --git a/src/mainboard/google/oak/tpm_tis.c b/src/mainboard/google/oak/tpm_tis.c index 018f02db10..ba019a6983 100644 --- a/src/mainboard/google/oak/tpm_tis.c +++ b/src/mainboard/google/oak/tpm_tis.c @@ -14,7 +14,7 @@ */ #include <gpio.h> -#include <tpm.h> +#include <security/tpm/tpm.h> #include "gpio.h" diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index d9f2f8ff11..f34dac0705 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -35,7 +35,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <cbfs.h> -#include <tpm.h> +#include <security/tpm/tpm.h> #include "ec/compal/ene932/ec.h" void pch_enable_lpc(void) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index d054b393c5..90313fb848 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -35,7 +35,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <bootmode.h> -#include <tpm.h> +#include <security/tpm/tpm.h> #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" |