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2021-07-26mb/google/dedede/var/pirika: Add USB2 PHY parametersAlex1 Kao
This change adds fine-tuned USB2 PHY parameters for pirika. BUG=192601233 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/google/dedede/var/cappy2: Generate SPD ID for supported memory partsSunwei Li
Add supported memory 'K4U6E3S4AA-MGCR' for cappy2 BUG=None TEST=Build the cappy2 board. Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie76a4dca607bb2c3261bbe5478209a43e8430591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26soc/intel/jasperlake: Set xHCI LFPS period sampling off timeBen Kao
Provide an option to set xHCI LFPS period sampling off time (SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0). If the option is set in the devicetree, the bits[7:4] in xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated. The host will sample LFPS for U3 wake-up detection when suspended, but it doesn't sample LFPS at all time due to power management, the default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS period sampling off time is not 0ms, the host may miss the device-initiated U3 wake-up and causes some kind of race condition for U3 wake-up between the host and the device. BUG=b:187801363, b:191426542 TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash the image to the device. Run following command to check the bits[7:4]: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Ben Kao <ben.kao@intel.com> Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/google/brya: move the common config to the baseboardZhuohao Lee
This patch moves the common config to the Kconfig under BOARD_GOOGLE_BASEBOARD_BRYA and removes the redundant config. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ie59299dfaba6bb23758d4a4c22a6dbbb4ba6520e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56387 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/brya: Enable BT offload conditionallySugnan Prabhu S
Currently, BT offload is disabled/enabled unconditionally based on the devicetree settings. BT offload uses I2S lines and cannot be enabled when a I2S based audio daughter card is active. So we need to enable BT offload only while using soundwire based audio daugther card. BUG=b:175701262 TEST=Verified BT offload on brya with soundwire audio daughter card BT offload enabled Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-24soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-24mb/google/guybrush: Update GPIOs settingsMartin Roth
- The WWAN card was being disabled later than desired. - The SD card was never being placed into reset on BoardID 1. - Enable Touchscreen power - Enable PCIe_RST1 at the same points as PCIe_RST - Remove Redundant Bootblock settings BUG=b:193036827 TEST=Build & Boot, look at GPIO states through boot process Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5431da755d98e4ad0b300d01cac562d61db0bc08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-23herobrine: get boardid from GPIO configurationRavi Kumar Bokka
Getting boardid information for the different SKU variants BUG=b:182963902, b:193807794 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-23mb/google/veyron: Remove references to EC firmware board namesPatrick Georgi
Chrome EC is relatively quick with retiring "old" boards from their tree so when upreving it, the last veyron in that list that wasn't commented out is gone as well. Change-Id: Ie1ef693c8d0947396ee01e5aa5f40ef36c8a317a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56430 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23mb/google/cherry: replace magic numbers by the I2C bus nameRex-BC Chen
When accessing I2C, we should use the official names (I2Cx) instead of magic numbers. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I17cc4c87f5ad26deeb5e529d1c106b697a53591b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56504 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/google/guybrush: Setup EC_IN_RW GPIO and export to payloadKarthikeyan Ramasubramanian
EC_IN_RW_OD signal is routed from Google Security Chip to GPIO_91 in the upcoming hardware build. The existing SD_EX_PRSNT signal is dropped in the upcoming hardware build because SD7 support is dropped. Export the EC_IN_RW GPIO for use by payload. BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the device can boot successfully in both recovery and normal mode. Cq-Depend: chromium:3043702 Change-Id: I8986ba007a2d899c510be61664d90430b8d2d384 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56493 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/google/dedede/var/cret: Add Wifi SAR for cretIan Feng
Add wifi sar for cret. BUG=b:194163601 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ic2f3dbc5822c1f4b1c935c87295ba9916e0e359e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-22mb/google/brya/variants/redrix: Configure GPIOs according to schematicsWisley Chen
Update initial gpio configuration for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I2294fb3bdba832677038cfe24b5014014c7f03e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56428 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mainboard/google/herobrine: Add configuration for SD card detect pinShaik Sajida Bhanu
Without this configuration, even though there is no SD card it shows as SD card is present and host controller waits for card to respond. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board with SD card and without SD card, make sure if SD card not present then host controller should not wait for card to respond. Change-Id: I5dc5ba10c98d606d98e7d4f4c41c3e4f45e94452 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21mb/google/brya/variants/primus: Update two GPIOsariel fang
1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function. 2. Set GPP_E21 as NC to remove LCLW_DET function BUG=b:190643562 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Program Unused Cnvi BT related GPIOs to NCMaulik V Vaghela
Program unused Cnvi BT UART GPIOs as NC since we are using Bluetooth over USB mode for Brya. Change-Id: I33a37ceb8a91603d2a193de5bdd1b6885eb3c319 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55317 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Create taeko variantKevin Chang
Create the taeko variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:193685558 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TAEKO Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: If738849bc3103c52a4c4d8a8aaef3f90a62ad5c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56385 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya/var/gimble: Include SPD for MT53E1G32D2NP-046 WT:A and ↵Mark Hsieh
K4U6E3S4AA-MGCR Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56329 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Add variant specific soc chip config updateSugnan Prabhu S
This patch adds support for variant specific soc chip config update function. Change-Id: Ic3a3ae0b409433e6dfa102c5e7a6322d4f78f730 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-21mb/google/octopus/variants/ampton: Resume from suspend on critical batteryJames Chao
This patch makes Ampton EC wake up AP from s0ix when the state of charge drops to 2%. Demonstrated as follows: 1. Boot Ampton. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 2. 4. System resumes. BUG=b:189540432 BRANCH=Octopus TEST=Verified on Ampton. Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350 Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56341 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the new memory parts used by primus and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:193813079 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-21mb/google/herobrine: Retrieve SKU ID from ECPhilip Chen
BUG=b:186264627 BRANCH=none TEST=build herobrine Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id3faf7af64c0129ec646a01085adc43b561225d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21mb/google/cherry: add mt6360 support for MT8195Rex-BC Chen
For new MT8195 devices we will control mt6360 via EC, so we have to add ec function of controlling MT6360 and add CONFIG to separate them. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic2228f5b45173f0905ea66a3a1f00ec820e0f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-21mb/google/cherry: initialize SD card reader using regulator interfaceRex-BC Chen
TEST=boot kernel from sd card pass on Cherry board. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic20a2f3f053130ded202cf5ec861450f0f18eed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56437 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/cherry: add mt6360 ids for regulator.cRex-BC Chen
Add MTK_REGULATOR_VCC and MTK_REGULATOR_VCCQ for regulator.c. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iedb1036da3c87106157c51cc46b52545faba102c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56436 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21soc/mediatek/mt8195: modify mt6360 interfaceRex-BC Chen
With the new definition of mt6360_regulator_id, merge the MT6360 LDO and PMIC interfaces into one. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-21soc/mediatek/mt8195: redefine mt6360_regulator_idRex-BC Chen
On MT8195 platforms with BC1.2, we have to use EC to control MT6360 so the mt6360_regulator_id is redefined to match the numbers defined in EC driver. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21Revert "mb/google/brya: Enable south XHCI ports 1 and 2"Tim Wawrzynczak
This reverts commit f7f715dff38c4a629139b2493ed6e0d7cc2eb36f. Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable BUG=b:184324979 TEST=boot brya, all 3 USB Type-C ports still enumerate devices Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56132 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-20mb/google/volteer/variants/collis: Fix pen ejection eventFrankChu
Modify PENH device GPIO GPP_E17 for pen ejection event. BUG=b:192511670,b:193093749 BRANCH=firmware-volteer-13672.B TEST=test pen insert and remove by evtest , SW_PEN_INSERT value 1 when insert pen to pen slot. SW_PEN_INSERT value 0 when remove pen from pen slot. Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ida5e5b35464471a7896cef392e178a3d2c0ea1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-07-19grunt/treeya: add Realtek ALC5682 codec supportKevin Chang
Replace audio codec from DA7219 to Realtek ALC5682. Add Realtek ALC5682 support. BUG=b:185972050 BRANCH=master TEST=check on treeya system ALC5682 audio codec is working normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-19mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h'Subrata Banik
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I411f4f2c237a9e2d39038ee30f2957698ee053bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-17mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:BFrank Wu
Add new ram_id:1000 for memory part MT40A1G16RC-062E:B. BUG=b:193732051 TEST=Generate new spd file and build coreboot. Then boot from the DUT with new memory MT40A1G16RC-062E:B Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17mb/google/volteer: Deduplicate lockdown configFelix Singer
The setting `chipset_lockdown` has the same configuration for all variants and they also match with the baseboard configuration. Thus, remove it from the variant overridetrees. Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17mb/google/volteer/baseboard: Configure chipset_lockdown separatelyFelix Singer
The configuration of the setting `chipset_lockdown` doesn't have any effect for most of the variants since their configuration of `common_soc_config` overwrites the configuration of the baseboard's devicetree. If `chipset_lockdown` is configured separately in the baseboard devicetree, the variant overridetrees reuse its configuration. Thus, move `chipset_lockdown` out of `common_soc_config` in the baseboard devicetree and configure it separately. Change-Id: I595c042cf62680d61f60965710d382bfdcd81671 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBERFelix Held
Before the part number for all boards was "Grunt". This patch adds the correct part number/name for all variants. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17FrankChu
Redefine GPIO_EC_IN_RW to GPP_F17 BUG=b:193091165 BRANCH=firmware-volteer-13672.B TEST=verify FAFT firmware_DevMode Pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-16mb/google/cherry: Allow payloads to enable USB VBUSYu-Ping Wu
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:193499785 TEST=emerge-cherry coreboot BRANCH=none Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-07-15google/trogdor: Enable SPI_FLASH_MACRONIXJulius Werner
We may want to use that flash vendor on future variants. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-15mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a defaultMartin Roth
To be able to enable & disable PSP_verstage in the saved .config file, the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a select to a default with a prompt. BUG=182477057 TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK, verify that VBOOT_STARTS_IN_BOOTBLOCK is set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14mb/google/cherry: add configuration for tomatoRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I972c70773d4d928e75098efbf78f174d7c3ebf50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-12mb/google/brya: Update generic device number for mipi_camera deviceVarshit B Pandya
If two generic devices use the same number, device coming later overrides the earlier device, as a result of this the static.c has only one device. In the case where we have UFC set to UFC_USB, this will result in no IPU device scope in SSDT, since its entry will be set to disbled after UFC probe. TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12soc/amd/{cezanne,common}: Enable IOMMU PCIe DeviceRaul E Rangel
This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12mb/google/brya,primus,voxel: Update controller field for tbt_dma entriesMaulik V Vaghela
We need to reference correct USB port number for driver to identify type-C port number correctly. BUG=b:189476816 BRANCH=None TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/kukui: Add a new config 'Munna'Sunway
Introduce a new board 'Munna' to Kukui family. BUG=None TEST=make # select Munna BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56169 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12mb/google/guybrush: enable psp_verstage by defaultKangheui Won
Select VBOOT_STARTS_BEFORE_BOOTBLOCK to turn on psp_verstage by default. BUG=b:182477057 TEST=boot guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12mb/google/brya/variants/primus: Update GPIO for PS8811 initCasper Chang
Route GPP_D14 to USB_A1_RT_RST_ODL for PS8811 init sequence BUG=b:193099675 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/brya: Create kano variantDavid Wu
Create the kano variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:193052432 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KANO Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/volteer/var/voema: Remove stop delay time for ELAN TSDavid Wu
Remove register "generic.stop_delay_ms" and measure data, it still can meet elan touchscreen specification that reset pull high to I2C time > 150ms (T3 > 150ms). BUG=b:185308246 TEST=Measure the T3 delay time is greater than 150ms on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A BUG=b:190818098, b:190874372, b:192052098 TEST=build Change-Id: I62ee401e43bef22b4b09f41ea59bbdbc479f293c Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55885 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya: Create redrix variantWisley Chen
Create the redrix variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192052098 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_REDRIX Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-08mb/google/brya0: Update the FIVR configurationsV Sowmya
This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-07mb/google/dedede/var/boten: Modify Wifi-SAR sku conditionstanley.wu
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR detect condition for boten/botenflex sku. BUG=b:186174768 TEST=build and test on boten/botenflex Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/sasukette: Configure I2C times for touchpadTao Xia
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390.4 kHz BUG=b:192601250 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen
According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30595 -> 30400 VDD Offset: 77 -> 317 SOC Slope : 24063 -> 23789 SOC Offset: 105 -> 94 BUG=b:190338440 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/56077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2021-07-05mb/google/dedede: Fix the pointer/address used in memcpyKarthikeyan Ramasubramanian
The caller is already passing the address to the required LTE reset and enable GPIO. During memcpy, the address to that pointer is used which will lead to copying undefined data. Fix the pointer/address used in memcpy. BUG=None BRANCH=dedede TEST=Build Kracko, Drawcia and Metaknight mainboards which use this function. Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Found-by: Coverity CID 1458053, 1458054. Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/google/brya/brya0: Enable CrashlogTim Wawrzynczak
brya0 is a reference and development platform, therefore it would be helpful to have Crashlog enabled. Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-05mb/google/brya: Add HANG_DETECT host event to EC S0ix wake maskTim Wawrzynczak
The brya EC supports S0ix hang detection, but it was not enabled in coreboot as well, masking that event out of S0ix, therefore add it in to the EC S0ix wake mask. TEST=After EC prints "Warning: Detected sleep hang! Waking host up!", the host actually wakes up Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-05mb/google/dedede/var/cret: Disable SDCard controllerDtrain Hsu
Cret doesn't support SDCard. Disable SDCard contorller for Cret. BUG=b:191232222 TEST=Build and boot to check lspci Cq-Depend: chromium:2993724 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02mb/google/dedede/var/magolor: Enable G2 touchscreen for magmaTyler Wang
Add G2 touchscreen support for magma. BUG=b:189852808 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3e032bff7f3e97f54f3e544035e862058ea0dbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2021-07-02mb/google/volteer/variants/eldrid: Include SPD for MT40A512M16TB-062E:RMark Hsieh
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R. Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated with MT40A512M16TB-062E:R DDR4 memory parts. BUG=b:192380070 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01mb/google/hatch/scout: update gpios and device treeJeff Chase
Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart BUG=b:187078663 TEST=boot scout BRANCH=none Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/google/brya: Swap P-sensor IRQEric Lai
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct P-sensor. BUG=b:192331122,b:181555900 TEST=check P-sensor driver can be probed without error. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/google/dedede: Create cappy2 variantSunway
Create the cappy2 variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192035460 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY2 Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/brya/variants/primus: Update mainboard properties for BB retimer ↵Casper Chang
upgrade This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:55348 BUG=b:191897776 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-01mb/google/dedede/var/drawcia: Add LTE modem support for drawperKevin Chiu
Add LTE modem to devicetree. Configure GPIO control for LTE modem by fw_config. Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:186393848 TEST=Build image and check with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/dedede/var/kracko: Update LTE USB port configurationTony Huang
Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:178092096 BRANCH=dedede TEST=Build and boot to OS to check LTE by modem status Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30mb/google/brya/variants/gimble: init overridetree for gimbleMark Hsieh
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf BUG=b:191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3f6875ef438b147436605629445d346a56896a87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30mb/google/brya/variants/primus: update gpiosCasper Chang
set GPP_C3 and GPP_C4 as NC since LAN function removal. BUG=b:190643562 Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30ec/google: Use EC_HOST_EVENT_NONERob Barnes
google_chromeec_get_event returns 0 for no event. Return EC_HOST_EVENT_NONE=0 to improve readability. BUG=b:184074997 TEST=Build and boot guybrush without error Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0Tao Xia
This change adds fine-tuned USB2 PHY parameters for storo. BUG=191089827 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30mb/google/dedede/var/storo: Enable Wifi SAR for storoTao Xia
BUG=b:190027970,b:178175837 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I7084f9b7be2b66adda2d9d5a83ce5dd9c31d01b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30mb/google/brya: Set GPP_B3 to APIC modeEric Lai
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict. BUG=b:181555900 TEST=check dmesg there are no IRQ request errors like below. genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1) Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-29mb/google/guybrush: Initialize WWAN for USB if requestedMartin Roth
To set the Fibocom 850-GL module to USB mode, it needs to be disabled when PCIe training happens, or it will automatically switch to PCIe mode. This patch makes sure it's shut down when training happens in FSP-M. It will be brought up in ramstage and will be available for USB enumeration later. BUG=b:187316460 TEST=Run lsusb from the OS and see that the Fibocom module is present on USB. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/guybrush: Update romstage power-on timings for PCIeMartin Roth
This configures the romstage portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe devices out of reset, both need to be brought hign. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/guybrush: Update bootblock power-on timings for PCIeMartin Roth
This configures the bootblock portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. Setting the PCIE Reset happens in coreboot instead of in the FSP. The Aux reset lines are anded with the PCIe RST line, so both have to be brought up together. On v1 of guybrush, the PCIe reset line also resets EC communication, so it must be brought up immediately on that version. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/herobrine: Add Senor and Piglin variantsShelley Chen
Add configs for Herobrine variants. Also enable ec sw sync as this should not be disabled by default. BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-29mb/google/guybrush: provide full range backlight settings to kernelPratik Vishwakarma
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:190443612 Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835 Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/brya0: Enable MIPI UFCVarshit B Pandya
1. Add 2 port 2 endpoint 2. Add support for OVTI5675 3. Guard entries in override device tree by FW_CONFIG MIPI UFC is on I2C2 This configuration is as per P2 schematics BUG=b:190674542 TEST=Build and Boot on Brya Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/guybrush: Configure eSPI requirements before setting it upMartin Roth
When initializing eSPI early, guybrush has requirements to configure the bus properly. Those are normally run in bootblock_mainboard_early_init, but when setting up eSPI early, those have not run yet. BUG=192100564 TEST=Build along with previous patch, eSPI works on guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/volteer/var/volet: add G2 touch supportSheng-Liang Pan
Enable G2 touchscreen support for Volet. BUG=b:185097280 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I907356448b5d5cbf3974717654ea09cd995962f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55835 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/blipper: Update devicetree and gpio settingZanxi Chen
To reduce power load, set unused GPIOs to NC and close unused interface in devicetree. GPIOs and interfaces are as below: GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07 Interface: I2C1/I2C3/I2C5 USB: port2_3/2_4/2_6 BUG=b:185044041 BRANCH=dedede TEST=Built bios and test, it reduces power load without affecting device function. Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com>
2021-06-28mb/google/brya0: Add FW_CONFIG for UFCVarshit B Pandya
UFC on brya can be USB or MIPI Add FW_CONFIG bit for this option Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-28mb/google/brya: Update mainboard properties for BB retimer upgradeMaulik V Vaghela
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:54292 BUG=b:186521258 TEST=Updated BB retimer FW from 3.4 to 3.5 without any device connected. Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/dedede/var/sasukette: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-28mb/google/dedede/var/cret: Add ssfc codec cs42l42 supportDtrain Hsu
Add cs42l42 codec support in cret. BUG=b:188623237, b:189073353 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/pirika: Update DPTF parametersAlex1 Kao
Update DPTF parameters from internal thermal team. BUG=b:190518303 BRANCH=None TEST=emerge-dedede coreboot Change-Id: I4005047e0c5f39a12c161a92fbd0afaaec1dc976 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/pirika: Support audio AMP auto modeAlex1 Kao
Support audio AMP selection with fw_config. BUG=b:188446060 BRANCH=None. TEST=built pass Change-Id: Idf0eb2a87bfa9665e61d185e37adb90987f3cefb Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/blipper: Enable ELAN touchscreenZanxi Chen
Modify driver from hid to generic(ELAN0001 that used generic driver without hid). BUG=b:191620724 BRANCH=dedede TEST=build bios and boot, touchscreen will work properly. Change-Id: Ife77d514d9906049f237edd169bc07bb53c48579 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
2021-06-26mb/google/brya/variants/primus: init overridetree for PrimusCasper Chang
init overridetree.cb based on the schematic ver MB_20210616C. BUG=b:191897776, b:191897775 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I185b36e34d24b703092e3798e91c70ce3912b11f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-25mb/google/{octopus,reef}: Fix size of SI_BIOS region in default.fmdMatt DeVillier
0xf7f000 - 0x1000 = 0xf7e000, not 0xf6f000. This fixes build failure when selecting the option to validate the layout using the flash descriptor (CONFIG_VALIDATE_INTEL_DESCRIPTOR) Test: build google/casta successfully with IFD validation selected Change-Id: I6df67f76f5d766a9f4f85ffc3e1f0de4a241f509 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55815 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the only memory parts used by primus for Proto build and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:186091208,b:189169995 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I423fd9ad4349c51c6e6b166734ae706509d6ac3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25mb/google/volteer/var/chronicler: add chronicler memory configuration and ↵Sheng-Liang Pan
gpio and devicetree settings add memory configuration for chronicler, based on schematic and gpio table, update gpio and devicetree settings for chronicler. BUG=b:187318819 BRANCH=None TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage verify bootable with chronicler Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Id5524b97a236dcc64d18ab1cd2ce13f6bb2d998f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55340 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/octopus: add audio codec into SSFC support for Garg/GarfourKevin Chiu
BUG=b:191213716 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/guybrush: Change ACPI HID for machine driverYu-Hsuan Hsu
To avoid from using same the name AMDI5682 as Zork, changing to use AMDI1019. The corresponding kernel change is on CL:2929864 BUG=b:189297564 TEST=Audio works with the corresponding kernel change. Cq-Depend: chromium:2929864 Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Change-Id: Ie89302f3b6cd3edb8253b909fde4722c2ea1e102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55508 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/brya: add generic LPDDR4 SPDs for GimbleMark Hsieh
Add Makefile.inc to include three generic LPDDR4 SPDs for the following parts for Gimble: DRAM Part Name DRAM ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) H9HCNNNCPMMLXR-NEE 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I60f95ac5ed7f3134882f6580335ec33632676796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25mb/google/brya/variants/gimble: set up gpioMark Hsieh
Set the GPIO configuration of gimble BUG=b:191213263 Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I667943578a2bf58cc5841564b8df5b6469d7594b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55717 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24mb/google/trogdor: Add new vaviant mrblandZanxi Chen
New boards introduced to trogdor family. BUG=b:191800434 BRANCH=none TEST=make Change-Id: I93b74e79188bd0cc36c8b48e552230ae0d6f593a Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-24soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik
This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24mb/google/guybrush: configure eSPI mux on psp_verstageKangheui Won
Temporarily set eSPI mux in verstage_mainboard_early_init. Ideally cezanne code should have common function to do this and mb-specific code would just call it, but for now PCI access doesn't work in the PSP so we can't do it. AMD team confirmed that the current PSP doesn't configure LPC so we don't have to disable LPC when configuring eSPI mux so we can temporarliy skip the LPC part here. BUG=b:183149183 TEST=boot guybrush with psp_verstage Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 07:25:13 +0000