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Add initial override devicetree for riven based on
the latest schematic (Riven(ZDK)_MB_Proto_0601.pdf).
1. Add eMMC DLL tuning value (copy from craask)
2. Configure I2C frequency (copy from craask)
3. Add audio codec and speaker amp settings
4. Add Elan touchscreen settings (copy from craask)
5. Add WFC and usb settings (copy from craask)
6 Add Elan and Synaptics touchpad settings (copy from craask)
7. Add WIFI6(CNVI) and WIFI7(PCIE) configuration
8. Add LTE settings (copy from craask)
BUG=b:337169542
TEST=Local build successfully.
Change-Id: I1dda3557edb44dda9c3a1efaf98437352978561c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83059
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Elan touchpad driver in newer linux kernels (>= 5.15) no longer
explicitly configures the touchpad as a wakeup source for devices
not using device tree. It is now assumed this information should be
extracted from ACPI, therefore we need to update drallion's devicetree
so that the device regains its lost capability.
TEST=update drallion FW and verify touchpad can cause wake up from
suspend
Change-Id: Iff21afda144cc11a013cb72816064df1c9eb21ae
Signed-off-by: Angela Czubak <aczubak@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enables ACPI brightness controls to be generated, and display
brightness controls to be functional under Windows.
TEST=build/boot Win11 on google/brya (craaskin), verify display
brightness controls present and functional.
Change-Id: I821b912cf52b5b89c5c9d831a5a15566b1b31639
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Boards using the brya baseboard already generate ACPI brightness
controls via their use of the gfx/generic driver, but need the
default brightness steps in order for display brightness control
to be functional under Windows.
TEST= build/boot Windows 11 on banshee, verify brightness controls
functional.
Change-Id: I03bb7a7309476839c49d2e862a036d9e89800605
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70372
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Lotso's WIFI_BT is same design as brox, copy from brox.
BUG=b:339612353
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I3946297db7f10a31570f773bdc5665f9f472c9fe
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83053
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Configure GPIOs according to schematic_20240607.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I760a7a234df43db3a557b3be9e20ff7aa5f80b72
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS which intends to achieve a unified AP firmware image across UFS and non-UFS skus.
BUG=b:328580882
TEST=Local build successfully.
Change-Id: Ifcee68a3492ab4606819de0be41701f803151f66
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83061
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Turn off camera power during s0ix to improve power consumption.
BUG=None
BRANCH=brya
TEST=built and verified GPP_A17 went to low during s0ix with a scope.
[Measurement of s0ix power consumption - 1 hour avg]
Before this: 301.4 mW
After this: 299.8 mW
Change-Id: Iae02d06e9f5a5988563b2b7ae36d153aecedb9d7
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83029
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Enable the fixed boot mode option in the VBT and set it to 1920x1080,
so that drobit boards equipped with 4K screens are legible at boot.
TEST=build/boot drobit w/4K screen using edk2 payload, verify boot
resolution set to 1080p and UEFI menus readable without a magnifying
glass.
Change-Id: If1f9e36d9bbdc2955ba890e2832aa64af9ba8f73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Generate RAM IDs for
K3KL6L60GM-MGCT
H9JCNNNBK3MLYR-N6E
K3KL8L80DM-MGCU
MT62F1G32D2DS-023 WT:C
H58G56BK8BX068
BUG=b:333494257
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: I7a240a263816193b9f3d418385c1673e9d3f89db
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
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Based on lotso EVT schematics update gpio settings.
GSPI0_CS0_L -> NF7
GSPI0_MISO -> NF7
GSPI0_MISO -> NF7
GPP_F18 -> EDGE_SINGLE
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I12d84538566c4d51fe346eb5609e55d91ddafbea
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
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Pujjoga support EM060 WWAN, use wwan_power.asl to handle the
power off sequence.
BUG=b:346479638
TEST=Build and boot on pujjoga
Change-Id: I1273d09385c661835d741691b3c4af26e72a9f86
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83042
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the P sensor does not work.
So add SX9324 registers settings based on tuning value from SEMTECH.
BUG=b:340749850
TEST=Check i2c register settings on Pujjoga and
confirm P sensor function can work by kernel 6.6 driver.
Change-Id: I205c1f5228d792afc763a06f74a8744918e2da75
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82689
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add AX211 wifi sar table for sundance wifi sar config.
Use fw_config to separate different wifi card settings.
WIFI_SAR_TABLE_AX211: 0
BUG=b:332978681
Test=emerge-nissa coreboot
Change-Id: Ide84996da567e4f866a2a1309a6976ed8df635a6
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83044
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add FW_CONFIG probe based on sundance boxster of below devices:
WWAN
Schematic version: NEC_SHIKIBU_ADL_N_MB_EVT_20240330
BUG=b:332978681
TEST=Boot to OS and verify the WWAN devices is set based on
fw_config.
Change-Id: I14339201d8ee21c85fefa96a49323e0c25cb8eca
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83041
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned.
BUG=b:345112878
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I1e5e49c1baa8d2b00134c26cc3b69aa15712b512
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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We use ALC256 as HDA codec on orisa. Add verb table and the
related device tree changes for HDA related registers.
BUG=b:338523452
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I92051886341bd317cce6061ece83439d156b0f90
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add override devicetree based on schematic_20240607.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Fill in memory config based on the the schematic_20240607.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I1456f7385e092b606fc0a35b25f3454600af8b23
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82662
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refer to the reference board of nivviks, and update GPIO settings
based on latest schematic (Riven(ZDK)_MB_Proto_0601.pdf).
BUG=b:337169542
TEST=Local build successfully.
Change-Id: Ic43c743fcc2ec89b5a9e2fbe1a87b833d59f1e74
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82973
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For each sandybridge boards with option to use MRC or native platform
init code, add a copy of the board's USB port config, consolidated between
both code paths, into the southbridge devicetree, using special values
allocated for this consolidation.
These get hooked up in a separate patch.
Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar table support for xol. Bit 31 in CBI/FW_CONFIG
is used to select different sar table (index 0 or 1) but only
0 is in used at the moment.
BUG=b:344274789
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: Id4dc74c4f2a807d2e531b419ecb7b590d4c32ac2
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Current existing temperature thresholds of TSR1 sensor are set at 60C
to start fan. Due to this CPU gets hot and temperature goes over 80C.
In this situation, fan does not even start to lower down CPU temperature.
With updated new settings based on tuning from thermal team, start fan
early at 40C for TSR0 and TSR1 so the CPU temperature stays below 80C.
BUG=b:339493551
TEST=Built and tested on google/brox board
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I4765c13c10e436733d8c9d017085968daa561ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82784
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change restores the EN_PP3300_SSD GPIO configuration in the
ramstage for the Rex0 variant. This is necessary to enable testing
of RO lockdown scenarios on FSI'ed Screbo devices, where bootblock
changes are not applicable.
Additionally, ensures locking the GPIO PAD from getting misconfigured
after booting to OS.
BUG=b/337971452
BRANCH=firmware-rex-15709.B
TEST=Able to boot google/rex with RO locked to an older version without
SSD GPIO refactored, and RW is with the latest revision.
Change-Id: Ia7564b14a20d00e9bb2c9466b7a737dd97f01351
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add AX211 and AX203 wifi sar table for pujjoga wifi sar config.
Use fw_config to separate different wifi card settings.
WIFI_SAR_TABLE_AX211: 0
WIFI_SAR_TABLE_AX203: 1
BUG=b:336167281
Test=emerge-nissa coreboot
Change-Id: If0f542cb13e93e99960bf65d616b26cee7617a43
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add FW_CONFIG probe based on pujjoga boxster of below devices:
WWAN
Schematic version: 500E_GEN4S_ADL_N_MB_0418
BUG=b:336167281
TEST=Boot to OS and verify the WWAN devices is set based on
fw_config.
Change-Id: I94cb9ffe47888a8b7b5c6837ddfc390a1d2e77d1
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add bookem new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Zilia SDVB8D8A34XGCL3N3T
BUG=b:344482259
TEST=Use part_id_gen to generate related settings
Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82783
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable type-c port 0 USB2 function.
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I0d7adc329a8c26941957d7a7472a5166b07bda5b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82903
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the
same value and conveys additional information to the reader. Done with a
bulk search and replace operation.
Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Based on lotso EVT schematics add dq map settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82600
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
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Based on lotso EVT schematics update gpio settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82573
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
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Set GSC_SOC_INT_ODL to GPP_A17 instead of GPP_A13.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82717
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set LpDdrDqDqsReTraining to 1 for xol. Value 0 will cause black screen
issue.
Reference: https://review.coreboot.org/c/coreboot/+/79527
> FSP default value for LpDdrDqDqsReTraining is 1. For boards
> that didn't set LpDdrDqDqsReTraining to any value, 0 was being
> assigned and it caused black screen issue.
BUG=b:332980211
BRANCH=brya
TEST=Built and verified there is no black screen issue during power
on/off test for over 100 cycles.
Change-Id: Ia346ce559b4509ea1a63abe28b12ad909f9b7b0d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82778
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Due to system spec change, change audio codec ALC5650 to ALC5682I-VS
BUG=b:329787697
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I38e5c58b3ef3fbe709b98601975ae3821bb77213
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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- Add Rex64 board to Kconfig menu
- Enable building for Rex64 with x86_64 support
Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Update used USB port[2][3](type-a) setting for nova.
BUG=b:328711879
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
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The devicetree entry and gpio.c updated as per the schematics of Trulo
to map the OC fault signals from A0/A1 USB ports.
BUG=b:335858378
TEST= Able to build google/trulo
Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
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Sundance support FM101 WWAN, use wwan_power.asl to handle the
power off sequence
BUG=b:343139385
TEST=Build and boot on sundance
Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Modify the Goodix touchscreen from new vendor and remove 3 unused
touchscreens. According to the information provided by the key-part
team.
BUG=b:340689681
TEST=Build and check Goodix touchscreen can work.
Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally.
According to Intel provides eMMC DLL delay patch that tuning on each
Sundance different eMMC system to modify some system can't boot to OS problem.
BUG=b:342057438
TEST=Build and check each SKU eMMC can work.
Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image.
This patch enables Sign of Life image during MRC training.
BUG=b:335369811
TEST=Able to boot to ChromeOS with SOL image.
CPU log:
[SPEW ] bootmode is set to: 0 (boot with full config)
[0.384818] DP PHY mode status not complete
[0.388911] DP PHY mode status not complete
[0.393197] DP PHY mode status not complete
[0.397484] DP PHY mode status not complete
[0.401771] DP PHY mode status not complete
[0.406057] DP PHY mode status not complete
[0.410345] DP PHY mode status not complete
[0.414632] DP PHY mode status not complete
[0.418916] DP PHY mode status not complete
[0.423203] DP PHY mode status not complete
[0.427491] DP PHY mode status not complete
[0.431777] DP PHY mode status not complete
[INFO ] Informing user on-display of memory training.
[DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes)
[WARN ] CBFS: 'preram_locales' not found.
[ERROR] ux_locales_get_text: preram_locales not found.
[DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes)
[INFO ] ELOG: NV offset 0xf20000 size 0x4000
elogtool list:
0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088
1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown
2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success
3 | 2024-05-10 02:27:09-0700 | System boot | 4
4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled
5 | 2024-05-10 02:27:11-0700 | System Reset
6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5
8 | 2024-05-10 02:27:36-0700 | System boot | 5
9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled
10 | 2024-05-10 02:27:37-0700 | System Reset
11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
|
|
This patch adds initial PCI device entries into the baseboard
devicetree.cb.
TEST=Able to build google/trulo.
Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid
prompting wrong dmesg as below.
```
usb usb2-port3: Cannot enable. Maybe the USB cable is bad?
```
Trulo variants to override the USB ports as per the target
board design.
TEST=Able to build google/trulo.
Change-Id: I6240e66ed3d1a7198c1a526fdca2483910157235
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch adds chip config entries for EC host cmd and memory map
ranges.
TEST=Able to build Google/Trulo.
Change-Id: Id4b0f3bba934c8da56b6d7ca8579b46b6cccac28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Adjust setting as recommended by power team.
Add ramstage.c in Makefile.inc to set psys_pl2_watts in
variant_devtree_update().
Also copy CPU power limit values from ovis baseboard.
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
check overrides setting
[INFO] CPU PsysPL2 = 178 Watts
[INFO] Overriding PsysPL2 (178)
[INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW)
(64000, 64000) PL4 (W) (120)
Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Adjust settings as recommended by thermal team.
Set PL1 max value tdp_pl1_override from 28W to 33W.
PL2, PL4 remain the same as CPU default.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust settings as recommended by thermal team.
Set tcc_offset value to 5 in devicetree.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:308704811#comment4.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch tries to simplify the baseboard/variant GPIO programming
for Google/Trulo. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.
With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.
BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant)
TEST=Able to build google/orisa.
Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
* Introduce a null check before calling `gpio_padbased_override`
in `variant_configure_pads`.
* This prevents potential errors in cases where the
`variant_gpio_override_table` function returns a null pointer,
indicating that there are no override pads to configure.
BUG=b:334826281
TEST=Able to avoid hang incase there is no GPIO override.
Change-Id: I733210a08091b37eda6e6b0d6924aafd5e7e6280
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82628
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Type-C kernel driver no longer programs the AP mux, as of
https://review.coreboot.org/c/coreboot/+/82077. So remove device
references to the TCSS Mux control device from the Type-C port driver.
This eliminates the following kernel error which was observed as a
result of the kernel trying to program muxes it no longer has control
over:
[ 4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95
[ 4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95
BUG=b:341331428
TEST=Run system reboot; configure mux kernel errors no longer seen.
Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1) Add all changes needed for early graphics
2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa
The InnoLux (N156HCN-EBA C7) panel is used for the device tree.
BUG=b:296433986
TEST=On-screen text message seen during MRC training on Craask
Logs:
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
[SPEW ] bootmode is set to: 0
[0.171409] DP PHY mode status not complete
[0.175509] DP PHY mode status not complete
[0.179799] DP PHY mode status not complete
[0.184087] DP PHY mode status not complete
[0.188376] DP PHY mode status not complete
[0.192665] DP PHY mode status not complete
[0.196954] DP PHY mode status not complete
[0.201243] DP PHY mode status not complete
[0.205532] DP PHY mode status not complete
[0.209821] DP PHY mode status not complete
[0.214110] DP PHY mode status not complete
[0.218397] DP PHY mode status not complete
[INFO ] Informing user on-display of memory training.
Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add Micron part MT62F512M32D2DR-031 WT:B only for Orisa.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
BUG=b:337178014
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I559ed817250c40795e6c613794d4f65c636f5fc5
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82586
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This reverts commit 7088257b1ab715e93506619727e3bf589ea688fb.
Reason for revert: Intel suggest is NC only.
No need to change anything that isn't broken.
Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82572
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This reverts commit f867c9c5473156617691d78350c362cd993bfcdd.
The new verb table breaks external mic detection on brox.
Revert and use old verb tables instead.
BUG=b:330433089
BRANCH=main
TEST=Verified headset on Brox
When connected to audiojack in power_save state of legacy hda driver,
headset is detected and audio is resumed.
Change-Id: I0d8c092de6166b2c62f5ecc3deaf4960128e6106
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82273
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Nova will use SOLDERDOWN. Add memory.c to override baseboard.
Update dram id table for correct platform parameter.
BUG=b:328711879
Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On GreenbayPOC, HDA Codec used is ALC236, different with Brox (ALC256)
Update to Realtek provided verb table for ALC236 audio codec.
BUG=b:336967284
TEST=Verified headset and audio workable on DUT with "rec" and
"aplay" command.
Change-Id: I9fbe57a0acab20387754f6b6cb5705e34c1c149b
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82413
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add devicetree settings per the schematic.
Differences to gladios:
1. remove SD reader
2. remove EMMC setting
3. modify USB port distribution
FRONT
-------------------------------------------------------
| A3 A1 |
| C0 A2 A0 |
-------------------------------------------------------
BACK
-------------------------------------------------------
| --------------- |
| | TX25A | |
-------------------------------------------------------
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81447
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Remove unused setting for retimer.
BUG=b:328711879
Change-Id: I48d8680d43a07aa3408dfbf5b25b568c2b51b343
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch removes VPU enablement code that is no longer needed because
the VPU is already enabled by default in the baseboard devicetree.
BUG=b:332488817
TEST=Able to see VPU PCI device in lspci list after booting
google/screebo to OS
Change-Id: I94de92e970be1548068ed4e19309a95129f041ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82423
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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This patch enables the Versatile Processing Unit (VPU) by default for
Rex/Ovis baseboard. VPU is a dedicated AI engine that is included in
the 14th generation "Meteor Lake" Core processors.
The VPU is designed to efficiently run AI models directly on the
system on chip (SoC). There is no power regression observed while
keeping the VPU default enabled to run AI models natively hence, this
patch enables the VPU by default.
BUG=b:332488817
TEST=Able to see VPU PCI device in lspci (0:11:0) list after booting
google/screebo to OS.
Change-Id: I8b3521c8ec613b002f971eaf9d346927fe8cd656
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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There is no direct way to override CPU default power_limits for
different SKUs.
This CL add structure variant_get_soc_power_limit_config() for
variants to define and configure the values of soc_power_limits_config
for current CPU SKU.
Variants can override these values i.e. pl1, pl2, psyspl2
in variant_devtree_update().
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
check overrides setting
Change-Id: Ib60fa4e3fc502d0aeb0c94ad46ba5a55b4dd027c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82199
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematic to update the gpio table.
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I3d01e3b9eaef72d9e143f5163ee49d8c8f455b5f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82412
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the orisa variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:337178014
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ORISA
Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.
Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add stop pin control for G2 touchscreen refer to
G7500_Datasheet_Ver.1.2.
BUG=b:335803573
TEST=build and verified touchscreen works normally
Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copy the data.vbt from brox to greenbayupoc
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematics GREENBAY_0412.SCH update the gpio and
devicetree settings.
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Cq-Depend:chrome-internal:7218819
Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01.
BUG=b:339756281
TEST=Build and check Focal touchpad can work.
Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix
H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these
parts.
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
H54G46CYRBX267 0 (0000)
BUG=b:337173071
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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|
Change-Id: I3aa669042908b92d7b270df077a352e197071780
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT
for riven as it has a VBT file now.
The VBT file is copied from the nivviks reference board.
BUG=b:337169542
TEST=build pass
Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable c1 state auto-demotion support for brox
BUG=None
BRANCH=None
TEST=Boot brox and verify in fsp debug logs
Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previous CL misspelling VR domain to IA not GT which cause
FVM Itrip(GT) not set correctly.
This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT)
has set to 54.
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
check overrides setting
IccLimit[1] = 216 ( 1/4 A)
Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Configure SODIMM settings for greenbayupoc. The SODIMM settings are
copied from mainboard/google/brya/variants/baseboard/brask/memory.c.
BUG=b:336955026, b:332230842
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS
using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM.
Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
1. MT62F1G32D4DR-031 WT:B (Mircon)
2. MT62F512M32D2DR-031 WT:B (Mircon)
3. H9JCNNNBK3MLYR-N6E (Hynix)
4. K3LKLKL0EM-MGCN (Samsung)
5. K3LKBKB0BM-MGCP (Samsung)
6. H9JCNNNCP3MLYR-N6E (Hynix)
BUG=b:337169542
TEST=build pass
Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.
BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.
Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Update the pad reset config for WLAN Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.
BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and
wakeup successfully using Wake on WLAN.
268 | 2024-05-07 13:56:44-0700 | S0ix Enter
269 | 2024-05-07 13:57:07-0700 | S0ix Exit
270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3
271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3
273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0
274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3
275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3
Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to Brox HW design, the PsysPmax is supposed to be 208W.
This patch changes PsysPmax setting from 21.5W to 208W.
Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903
Signed-off-by: Lawrence Chang <lawrence.chang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
|
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The smbus subsystem ID was inadvertently reversed when added in commit
6974bcd28e74 ("mb/google/parrot: override SMBus subsystem ID"), so
correct it.
TEST=build/boot Win10 on parrot, verify touchpad driver functional.
Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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The smbus subsystem ID was inadvertently reversed when added in commit
a6076cfcfdbe ("mb/google/butterfly: override SMBus subsystem ID"), so
correct it.
TEST=build/boot Win10 on butterfly, verify touchpad driver functional.
Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new Kingler follower 'Squirtle'.
BRANCH=corsola
BUG=b:333826091
TEST=emerge-corsola coreboot
Change-Id: I393738fc470ffc907f125647a46bf81c243708d7
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add data.vbt files for bujia supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.
changes:
1. "integrated DisplayPort with HDMI/DVI compatible"
-> "Integrated HDMI/DVI".
2. turn the AUX off.
BUG=b:327549688
TEST=build/boot various brya variants
Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81553
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brox uses PDC<->PMC direct connection for USBC mux configuration. Select
SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This
patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be
selected only when PDC<->PMC direct connection and CHROMEOS is not used.
BUG=b:332383540
TEST=USB3 plugged during G3, is detected after system boots from G3.
Cq-Depend: chromium:5484387
Cq-Depend: chrome-internal:7106592
Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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For Mithrax and Felwinter, port C1 is on the left side and port C2 is on
the right side. Correct the values accordingly.
The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports.
BUG=b:321051330
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT
Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
|
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Within ec_acpi.c, USB-C ports are iterated to be matched with
corresponding mux. The iteration happens from 0 to the number of USB-C
ports. Given iteration index i, the port with PLD group_token of (i+1)
is matched with mux_conn[i].
Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2
to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token
of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus,
follow the convention to add conn1 to mux_conn[0] and conn2 to
mux_conn[1].
Otherwise, the kernel subsystem linking between Type C connector and USB
mux will be swapped.
BUG=b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT.
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
usbpd lines are workaround for devices without firmware patch to
connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875
Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
|
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Configure eMMC DLL tuning values for Sundance board Samsung sku.
BUG=b:337741162
TEST=Use the value to boot on Sundance successfully.
Change-Id: I5f1e03c06c9f8567e757fed999730dff2551f1e0
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.
Change-Id: I49f5fda5628b2ebc76cd8db20c8f7fe85c676c7a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.
Change-Id: I38f46949d36359826317252e8d3434ad1b24382d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82156
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.
Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82155
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.
Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Fill GPIO table for pujjoga.
BUG=b:336469694
TEST=emerge-nissa coreboot
Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82044
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Update TDP PL1 value for the DTT optimization. The new value 18W is from
internal thermal/performance team.
- tdp_pl1_override: 15 -> 18 (W)
BUG=b:336684032
BRANCH=brya
TEST=built and verified MSR PL1 value.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
After this patch:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update I2C5 timing parameter values to meet I2C bus spec.
- fall_time_ns: 400 -> 200
BUG=None
BRANCH=brya
TEST=built and measure I2C5 timing parameters
Before:
tLOW : 1.88 us (spec >= 1.30)
tHIGH: 0.57 us (spec >= 0.60)
fSCL : 399.80 KHz
After:
tLOW : 1.60 us (spec >= 1.30)
tHIGH: 0.97 us (spec >= 0.60)
fSCL : 392.1 KHz
Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Create the riven variant of nissa reference board by copying the
template files to a new directory named for the variant.
The riven variant is a twinlake platform.
BUG=b:337169542
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RIVEN
Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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