diff options
| author | Eren Peng <peng.eren@inventec.corp-partner.google.com> | 2024-04-26 11:05:05 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-14 13:08:30 +0000 |
| commit | bb616ca4830f6bf483abfc99c0b5c39ae64f56c7 (patch) | |
| tree | a4bd2602615b6d213c305f82b2ee686bdf488f2d /src/mainboard/google | |
| parent | d05611d264b5dcf4223f927bf88c6504fb04f3f7 (diff) | |
mb/google/brox/var/greenbayupoc: Update devicetree and gpio settings
Based on latest schematics GREENBAY_0412.SCH update the gpio and
devicetree settings.
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Cq-Depend:chrome-internal:7218819
Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Diffstat (limited to 'src/mainboard/google')
6 files changed, 373 insertions, 3 deletions
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 908612d68b..00a0509d74 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -70,6 +70,7 @@ config BOARD_GOOGLE_LOTSO config BOARD_GOOGLE_GREENBAYUPOC select BOARD_GOOGLE_BASEBOARD_BROX + select CHROMEOS_WIFI_SAR if CHROMEOS select MEMORY_SODIMM if BOARD_GOOGLE_BROX_COMMON diff --git a/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk index be05cd4e5c..a5ee3624fd 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk +++ b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk @@ -1,3 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c +romstage-y += gpio.c romstage-y += memory.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/greenbayupoc/gpio.c b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c new file mode 100644 index 0000000000..f26f098e9d --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: E3110FFB1FCDA587 + * Overrides: None + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */ + PAD_NC(GPP_A19, NONE), + /* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */ + PAD_NC(GPP_A20, NONE), + + /* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX + * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */ + PAD_NC(GPP_D9, NONE), + /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX + * NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */ + PAD_NC(GPP_D10, NONE), + + /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + + /* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */ + PAD_NC(GPP_H15, NONE), + /* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */ + PAD_NC(GPP_H17, NONE), + + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb index aeb4de594b..1939325e44 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb +++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb @@ -1,14 +1,201 @@ fw_config - field STORAGE 0 1 + field RETIMER 0 1 + option RETIMER_UNKNOWN 0 + option RETIMER_BYPASS 1 + end + field STORAGE 2 3 option STORAGE_UNKNOWN 0 - option STORAGE_UFS 1 - option STORAGE_NVME 2 + option STORAGE_NVME 1 + option STORAGE_UFS 2 + end + field WIFI 4 + option WIFI_CNVI_WIFI 0 + option WIFI_BT_PCIE 1 + end + field UFC 5 + option UFC_NONE 0 + option UFC_USB 1 + end + field AUDIO 6 7 + option AUDIO_UNKNOWN 0 + option AUDIO_REALTEK_ALC3247 1 end end chip soc/intel/alderlake + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI) device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + probe STORAGE STORAGE_UNKNOWN + end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI WIFI_BT_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI WIFI_BT_PCIE + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI WIFI_CNVI_WIFI + end device ref smbus on end end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c new file mode 100644 index 0000000000..b468320356 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/variant.c b/src/mainboard/google/brox/variants/greenbayupoc/variant.c new file mode 100644 index 0000000000..9452ad0eb9 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/variant.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI))) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + } +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} |