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2024-05-14mb/google/nissa/var/quandiso: Add stop pin for G2 touchscreenRobert Chen
Add stop pin control for G2 touchscreen refer to G7500_Datasheet_Ver.1.2. BUG=b:335803573 TEST=build and verified touchscreen works normally Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Add vbt from broxEren Peng
Copy the data.vbt from brox to greenbayupoc BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Update devicetree and gpio settingsEren Peng
Based on latest schematics GREENBAY_0412.SCH update the gpio and devicetree settings. BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Cq-Depend:chrome-internal:7218819 Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455 Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-14mb/google/nissa/var/sundance: Update HID offset to 0x01 for Focal touchpadLeo Chou
Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01. BUG=b:339756281 TEST=Build and check Focal touchpad can work. Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14mb/google/dedede/var/pirika: Add SPD IDs for two new memory partsDaniel_Peng
Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) H54G46CYRBX267 0 (0000) BUG=b:337173071 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-13mb/google/rambi: Use <device/dram/ddr3.h>Elyes Haouas
Change-Id: I3aa669042908b92d7b270df077a352e197071780 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/{eve,glados}: Use <spd.h> and <dram/ddr3.h>Elyes Haouas
Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-13mb/google/brya/var/riven: Copy VBT data file from nivviksDavid Wu
Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT for riven as it has a VBT file now. The VBT file is copied from the nivviks reference board. BUG=b:337169542 TEST=build pass Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/brox: Disable c1 state auto-demotionAshish Kumar Mishra
Disable c1 state auto-demotion support for brox BUG=None BRANCH=None TEST=Boot brox and verify in fsp debug logs Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12mb/google/rex/var/deku: Correct FVM Itrip for GT VR domainTony Huang
Previous CL misspelling VR domain to IA not GT which cause FVM Itrip(GT) not set correctly. This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT) has set to 54. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting IccLimit[1] = 216 ( 1/4 A) Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-12mb/google/brox/var/greenbayupoc: Configure board for SODIMM useEren Peng
Configure SODIMM settings for greenbayupoc. The SODIMM settings are copied from mainboard/google/brya/variants/baseboard/brask/memory.c. BUG=b:336955026, b:332230842 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM. Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-12mb/google/brya/var/riven: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. 1. MT62F1G32D4DR-031 WT:B (Mircon) 2. MT62F512M32D2DR-031 WT:B (Mircon) 3. H9JCNNNBK3MLYR-N6E (Hynix) 4. K3LKLKL0EM-MGCN (Samsung) 5. K3LKBKB0BM-MGCP (Samsung) 6. H9JCNNNCP3MLYR-N6E (Hynix) BUG=b:337169542 TEST=build pass Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-08mb/google/brox: Fix the pad reset config for WLAN Wake interruptKarthikeyan Ramasubramanian
Update the pad reset config for WLAN Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and wakeup successfully using Wake on WLAN. 268 | 2024-05-07 13:56:44-0700 | S0ix Enter 269 | 2024-05-07 13:57:07-0700 | S0ix Exit 270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3 271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3 273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0 274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3 275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3 Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-08mb/google/brox/var/brox: increase PsysPmax from 21.5W to 208WLawrence Chang
According to Brox HW design, the PsysPmax is supposed to be 208W. This patch changes PsysPmax setting from 21.5W to 208W. Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903 Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08mb/google/parrot: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit 6974bcd28e74 ("mb/google/parrot: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on parrot, verify touchpad driver functional. Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08mb/google/butterfly: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit a6076cfcfdbe ("mb/google/butterfly: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on butterfly, verify touchpad driver functional. Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07mb/google/corsola: Add new board variant SquirtleYang Wu
Add a new Kingler follower 'Squirtle'. BRANCH=corsola BUG=b:333826091 TEST=emerge-corsola coreboot Change-Id: I393738fc470ffc907f125647a46bf81c243708d7 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-06mb/google/brya/var/bujia: Add VBT data fileShon Wang
Add data.vbt files for bujia supported by brask recovery images. Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file. changes: 1. "integrated DisplayPort with HDMI/DVI compatible" -> "Integrated HDMI/DVI". 2. turn the AUX off. BUG=b:327549688 TEST=build/boot various brya variants Change-Id: Id56461708250eaedd288ddbf788d686153df0b96 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81553 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATIONKrishna Prasad Bhat
Brox uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be selected only when PDC<->PMC direct connection and CHROMEOS is not used. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-06mb/google/brya: Correct _PLD valuesWon Chung
For Mithrax and Felwinter, port C1 is on the left side and port C2 is on the right side. Correct the values accordingly. The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports. BUG=b:321051330 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06mb/google/brya: Fix mux_conn index used by ec/google/chromeecWon Chung
Within ec_acpi.c, USB-C ports are iterated to be matched with corresponding mux. The iteration happens from 0 to the number of USB-C ports. Given iteration index i, the port with PLD group_token of (i+1) is matched with mux_conn[i]. Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2 to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus, follow the convention to add conn1 to mux_conn[0] and conn2 to mux_conn[1]. Otherwise, the kernel subsystem linking between Type C connector and USB mux will be swapped. BUG=b:329657774 b:121287022 b:321051330 b:204230406 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT. TEST=Manually check that usb-role-switches are mapped to the correct port. Attach USB 3 A to C cable from development machine to left port of DUT. Attach nothing to right-hand port. usbpd lines are workaround for devices without firmware patch to connect superspeed lines. ectool usbpd 0 none ectool usbpd 0 usb ectool usbpd 1 none ectool usbpd 1 usb echo host > /sys/class/typec/port0/usb-role-switch/role (should succeed) echo host > /sys/class/typec/port1/usb-role-switch/role (should fail as no cable attached) Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875 Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06mb/google/nissa/var/sundance: Use default eMMC DLL settingLeo Chou
Configure eMMC DLL tuning values for Sundance board Samsung sku. BUG=b:337741162 TEST=Use the value to boot on Sundance successfully. Change-Id: I5f1e03c06c9f8567e757fed999730dff2551f1e0 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/sarien: Make use of chipset dt reference namesFelix Singer
Replace the PCI numbers with the reference names from the chipset devicetree. Also, remove their comments since they are superfluous now. Change-Id: I49f5fda5628b2ebc76cd8db20c8f7fe85c676c7a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06mb/google/sarien: Remove dt entries equal to chipset dtFelix Singer
Clean up the devicetree by removing entries which are equal to the chipset devicetree. The P2SB device is enabled but it's hidden by the FSP. So just remove that as well since the chipset devicetree configures it correctly. Change-Id: I38f46949d36359826317252e8d3434ad1b24382d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82156 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/drallion: Make use of chipset dt reference namesFelix Singer
Replace the PCI numbers with the reference names from the chipset devicetree. Also, remove their comments since they are superfluous now. Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82155 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/drallion: Remove dt entries equal to chipset dtFelix Singer
Clean up the devicetree by removing entries which are equal to the chipset devicetree. The P2SB device is enabled but it's hidden by the FSP. So just remove that as well since the chipset devicetree configures it correctly. Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06mb/google/brya/var/pujjoga: Add GPIO tableleo.chou
Fill GPIO table for pujjoga. BUG=b:336469694 TEST=emerge-nissa coreboot Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82044 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06mb/google/brya/var/xol: Override TDP PL1 valueSeunghwan Kim
Update TDP PL1 value for the DTT optimization. The new value 18W is from internal thermal/performance team. - tdp_pl1_override: 15 -> 18 (W) BUG=b:336684032 BRANCH=brya TEST=built and verified MSR PL1 value. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) After this patch: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/brya/var/xol: Tune I2C5 timing parametersSeunghwan Kim
Update I2C5 timing parameter values to meet I2C bus spec. - fall_time_ns: 400 -> 200 BUG=None BRANCH=brya TEST=built and measure I2C5 timing parameters Before: tLOW : 1.88 us (spec >= 1.30) tHIGH: 0.57 us (spec >= 0.60) fSCL : 399.80 KHz After: tLOW : 1.60 us (spec >= 1.30) tHIGH: 0.97 us (spec >= 0.60) fSCL : 392.1 KHz Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-06mb/google/nissa: Create a riven variantDavid Wu
Create the riven variant of nissa reference board by copying the template files to a new directory named for the variant. The riven variant is a twinlake platform. BUG=b:337169542 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_RIVEN Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/corsola: Sort Kconfig board selection in alphabet orderYidi Lin
Change-Id: Iefe61d3ad51d355806716483248df5b1083b69bc Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82149 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/google/nissa/var/pujjoga: Generate SPD IDsroger2.wang
Add pujjoga supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:337990338 TEST=Use part_id_gen to generate related settings Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82135 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06mb/google/nissa/variant/pujjoga: Update devicetree settingsroger2.wang
Based on schematic of 500E_GEN4S_ADL_N_MB_0418, generate overridetree.cb settings for Pujjoga. BUG=b:337611700 TEST=FW_NAME= pujjoga emerge-nissa coreboot chromeos-bootimage Change-Id: I279f94044a22f25100a44b1abe2ef5fb6d0dd835 Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82109 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06mb/google/rex/var/deku: Update psys_pmax_watt value to 180WTony Huang
Adjust setting is from power team. Change from 172W to 180W BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting Change-Id: Icc8b12adc9fb9f680b05131c8d41212865223ca9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-06mb/google/rex/var/deku: Update FVM itrip for VR domainTony Huang
Adjust setting is from power team. Itrip(GT) FVM 54 Itrip(SA) FVM 27 BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting Change-Id: I6d6cf7cecaac650a7b1784833b4afb8dffb3db2c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82176 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03mb/google/brya/var/xol: Update board type to BOARD_TYPE_ULT_ULXSeunghwan Kim
Correct .UserBd field to BOARD_TYPE_ULT_ULX from BOARD_TYPE_MOBILE. This is from Intel's guidance for MRC to map the memory speed to proper POR number. BUG=b:332980211 BRANCH=brya TEST=Built and compare the results of command 'dmidecode -t 17' [Before] (Same values in all of memory device handle) Speed: 6400 MT/s Configured Memory Speed: 6400 MT/s [After] (Same values in all of memory device handle) Speed: 5200 MT/s Configured Memory Speed: 5200 MT/s Change-Id: Id16bcbc2d0cb4c2cf3008cf2ef1027ed98e93afb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-03mb/google/corsola: Initialize USB port 0Wentao Qin
The default MT8186 platform is to initialize USB3 port 1. Use option bit 27 in fw_config to enable initialization of USB2 port 0 to support devices mounted on it. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_tableSeunghwan Kim
Add GPP_F18 configuration in early_gpio_table. Without this, DUT cannot get the proper state of this signal on early phase. It allowed DUT to attempt to enter into dev mode when EC is in RW currently, it causes the failure of autotest/firmware_DevMode. BUG=b:337365524 TEST=built and run autotest firmware_DevMode Change-Id: I2179bb10b431547bc35f332c74915a63495b779d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-04-30mb/google/brox: Add 20K pulldown to GPP_D14Shelley Chen
GPP_D14 is floating when ISH is not being used and wasting power. Add pulldown to prevent this from happening. BUG=b:336654954 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage make sure OS boots up HW team validated that power usage is 20 mW lower Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-29mb/google/brox: Fix the pad reset config for Touchpad interruptKarthikeyan Ramasubramanian
Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup using Trackpad. 246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3 247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3 248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67 249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3 250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3 251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67 Also suspend to S0ix and wakeup using Trackpad. Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-29mb/google/brya/xol: Add Fn key scancodeAseda Aboagye
The Fn key on Xol emits a scancode of 94 (0x5e). BUG=b:327656989 TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-26mb/google/rex: remove duplicate config for karisYH Lin
Remove duplicate config entry CHROMEOS_WIFI_SAR as it is used at the baseboard. BUG=None TEST=emerge-rex coreboot Change-Id: Iabf0e490103c2097f3f033036839b77b5a0bb1b3 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81226 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-25mb/google/brox/var/lotso: Add fw_config field for storagetongjian
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333494257 TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage Change-Id: Idb62e3f37e1480979ae529692455beb533434520 Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82056 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel moduleDaniel_Peng
1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module. 2.Describe the FW_CONFIG probe for the settings on glassway. - WIFI_SAR_0 for Intel Wi-Fi module AX211 BUG=336051631 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81781 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/brya/var/nova: Add initial configurationsKenneth Chan
Upload initial configuration for nova based on proto schematics. Memory: SAMSUNG 2G*4 K4U6E3S4AB-MGCL HYNIX 2G*4 H9HCNNNBKMMLXR-NEE BUG=b:328711879 TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-04-25mb/google/nissa/var/yaviks: Add stop pin for G2 touchscreenWisley Chen
Add stop pin control for G2 touchscreen BUG=b:335803573 TEST=build and verified Touchscreen work normally Change-Id: I7e0bbc7722cdda6bcca0485009fcf8510b1f55e2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81971 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panelYang Wu
Add STA_ER88577 MIPI panel for Wugtrio. Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82055 Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-24mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jackJianeng Ceng
Add a new GPIO port cbj-sleeve for kernel driver to call. At the same time, a new rt5645 driver is added to replace the generic driver to parse gpio. After entering the system, it is pulled high by the kernel to enable the MIC function. BUG=None TEST=MIC function is normal Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81774 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-23mb/google/rex/var/deku: Update USB _PLD valuesTony Huang
Fix custom_pld for USB2-C2 and USB3-C3 with same PLD group. Update USB2-A4 PLD group token. USB2/USB3 Type-C Port C2 "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))" USB2/USB3 Type-C Port C3 "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))" BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST= emerge-ovis coreboot Change-Id: Ieecf0f7dda671a421e4e4a4adbf83240fadd018d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-23mb/google/rex/var/deku: Configure GPIOTony Huang
Set unused pin to NC internal PU 20K BUG=b:325674908 BRANCH=firmware-rex-15709.B TEST= emerge-ovis coreboot Change-Id: I78eddaa41c14721eeb6ff33a4cb15382853e430b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-22mb/google/nissa/var/craaskov: modify 6W and 15W DPTF parametersIan Feng
The DPTF parameters were defined by the thermal team. Based on thermal table in 330817690#comment33. Set 6w "tcc_offset" to "15" by fw_config. BUG=b:330817690, b:290705146 BRUNCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I19100d960919dc3087fd067c24659de467eea276 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81997 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-04-19mb/google/brox/variants/lotso: add missing hda_verb.hFelix Held
Commit 00b40090aecf ("mb/google/brox: Move hda verb to variant dir") introduces a variant-specific file for the HDA verb tables, which commit 1bf0c3f1897c ("mb/google/brox: Create lotso variant") was missing which caused the build to fail when both patches were submitted. To fix the tree, add this file to the newly created lotso variant. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8a85115a204d9d9447a58da71eb65b1de963023d Reviewed-on: https://review.coreboot.org/c/coreboot/+/82014 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-19mb/google/brox: Create lotso variantKun Liu
Create the lotso variant of the brox reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:333494257 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_LOTSO Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-19mb/google/brox: Move hda verb to variant dirtongjian
Others variant boards might use diff HDA Codec, so move hda verb to brox variant dir. BUG=b:314702466 BRANCH=None TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Device list: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ALC256 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Headphone detection: evtest 8 Event: time 1713404716.656768, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1713404716.656768, -------------- SYN_REPORT ------------ Event: time 1713404722.802661, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0 Event: time 1713404722.802661, -------------- SYN_REPORT ------------ Change-Id: Id987c248c37dc8bdc63be7a2513fa8997b5ddc33 Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81945 Reviewed-by: Poornima Tom <poornima.tom@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-19mb/google/brox/var/greenbayupoc: Add fw_config field for storageEren Peng
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config field to prevent depthcharge build break. BUG=b:333325006 TEST=emerge-brox coreboot depthcharge with no errors Change-Id: I0e220787d6ac73ec8fa2469ed958981d0801920e Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-04-18mb/google/nissa/var/glassway: Add SPD IDs for two new memory partsDaniel_Peng
Support Memory for Hynix H58G66AK6BX070 and Samsung K3KL9L90CM-MGCT in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign H58G66AK6BX070 4 (0100) K3KL9L90CM-MGCT 5 (0101) BUG=b:335341310 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: Ic07ec36a8015ce6433196a93e894b818a515b954 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81955 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
2024-04-17mb/google/brox: Enable SAGvAshish Kumar Mishra
Enable SaGv support for brox BUG=None BRANCH=None TEST=Boot brox with SAGv enabled and verify in fsp debug logs Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-17mb/google/brya: Enable UFS driver for edk2 payloadMatt DeVillier
Several brya-based boards use UFS for storage, so enable the edk2 UFS driver when using the edk2 payload. TEST=build/boot google/brya (banshee, craaskov), verify internal boot media functional with edk2 payload. Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81871 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-17mb/google/zork: Enable eMMC driver for edk2 payloadMatt DeVillier
Several zork-based boards use eMMC for storage, so enable the edk2 eMMC driver when using the edk2 payload. TEST=build/boot google/zork (morphius, vilboz), verify internal boot media (both eMMC and NVMe) functional with edk2 payload. Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-17mb/google/corsola: Add new board variant VeluzaFrank Wu
Add a new Krabby follower device 'Veluza'. BUG=b:333630131 BRANCH=corsola TEST=none Change-Id: Idedcbfbddd6d98a51cf28a0963d68f6d8c68382c Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81791 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-16mb/google/nissa/variant/sundance: Modify i2c device for touch deviceLeo Chou
1. Remove non-use i2c address 0x10, 0x24 and 0x40 of touch IC for touch screen 2. Add new i2c address 0x5d of Goodix touch IC for touch screen 3. Add new i2c address 0x38 of Focal touch IC for touch pad BUG=b:333804572 TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage Change-Id: I8e2c60820a07b99b69860fd4f6557b448aef2341 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-16mb/google/nissa: Create pujjoga variantLeo Chou
Create the pujjoga variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:333839287 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOGA Change-Id: Ia8eb11eb65f9013e83abd45eefe7705d05b8697e Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81891 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-15mb/google/zork: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot zork (morphius) with SMMSTORE enabled. Change-Id: Ifd3be9b0757e270d2f106e2fbebf3991e49dec65 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/google/skyrim: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot skyrim (frostflow) with SMMSTORE enabled. Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/google/myst: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81867 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15mb/google/guybrush: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot guybrush (dewatt) with SMMSTORE enabled. Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/google/fizz: Use variant-specific gma-mainboard.ads filesMatt DeVillier
The karma variant, being a Chromebase, has an internal eDP output for the built-in display whereas the fizz/endeavour variants do not. Use separate gma-mainboard.ads files so that karma's internal panel works properly with libgfxinit. TEST=build google/fizz (fizz/karma) with libgfxinit enabled, ensure correct gma-mainboard.ads file is included in the build. Change-Id: Ia6aca538ba8c13b48aa80901222071d704b5f0c0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-15mb/google/brox: Create greenbayupoc variantEren Peng
Create the greenbayupoc variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:329530883 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_GREENBAYUPOC. Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-15mb/google/corsola: Add new board variant SkittyHerbert Wu
Add a new Krabby follower device 'Skitty'. BUG=b:331702790 TEST=emerge-corsola coreboot chromeos-bootimage BRANCH=corsola Change-Id: I2f12bccfda591a5baf8d23d217b6f1f81b059d15 Signed-off-by: Herbert Wu <herbert1_wu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81772 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Geoffrey Chien <geoffrey_chien@pegatron.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2024-04-13mb/google/beltino: Set initial fan PWM to 30%Matt DeVillier
Recent changes to the ITE 8772F SIO code caused the initial fan PWM to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot google/beltino to payload, verify fan noise is negligible. Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81513 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13superio/ite: Unify it8772f with common codeJoel Linn
The it8772f is now configured by the much better common code that is used for other chips in the family as well. This mainly concerns the EC, the GPIO functionality was not moved to common as it currently lacks a sane abstraction in any codebase. The datasheets of the it8772e(f) and it8728f (for reference) were studied and verified against the common code, adding exceptions where needed. Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-12mb/google/brox: Initialize NOTE_BOOK_MODE GPIOShelley Chen
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also initializing it (if ISH is enabled) to be NF2 (ISH_GP4). Also took the liberty of alphabetizing all the ISH GPIOs to they're easier to search through. BUG=b:316421831 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Make sure that brox device still boots up with this change. Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81789 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12mb/google/brya/var/sundance: Add GPIO tableLeo Chou
Fill GPIO table for Sundance. BUG=b:327520553 TEST=emerge-nissa coreboot Change-Id: I53ed5874347006985ca5231d1531fa519088f796 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81613 Tested-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-11tree: Drop unused <edid.h>Elyes Haouas
Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11mb/google/nissa/var/craaskov: Disable external fivrIan Feng
In next phase, craaskov will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:330253778 TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS work normally. Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-11mb/google/karis: Add FW_CONFIG and device for VPUJamie Ryu
BUG=b:333605309 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared. Change-Id: I6e2230715d783ea7108d71699fd19684ce19e2ff Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-11mb/google/brya: Create trulo variantDinesh Gehlot
This patch adds a new variant trulo for the baseboard trulo. BUG=b:333314089 TEST=abuild -a -x -p none -t google/brya Change-Id: I91157d252ef56c8938bfc08ed0f734c5dc7e614d Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81627 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-04-11mb/google/brya: Add new baseboard truloDinesh Gehlot
This patch adds a new baseboard trulo. This commit is a stub which only adds the minimum code needed for a successful build. BUG=b:333314089 TEST=abuild -a -x -p none -t google/brya Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10tree: Drop unused <elog.h>Elyes Haouas
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10tree: Drop unused <stdio.h>Elyes Haouas
Change-Id: I26c2abfce3417ed096d945745770fcae91a1e4ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81814 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10mb/google/corsola/var/wugtrio: Correct the display orientationYang Wu
Set orientation of KD_KD101NE3_40TI to LB_FB_ORIENTATION_RIGHT_UP to align the volume up/down direction with menu up/down in FW screen. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage, and check FW screen on wugtrio, test volume key behaves as expected. BRANCH=corsola Change-Id: Ie101cc8b983d3d16587f88fa787ed622e59d27eb Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81752 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10mb/google/brya: Remove baseboard-specific FMD namesDinesh Gehlot
This patch renames the 16MB FMD file to remove the baseboard-specific name 'Nissa'. This allows other supported baseboards to utilize the 16MB SPI flash. Additionally, the patch attempts to create a generic, unified 32MB FMD file for both brya and nissa variants. BUG=b:333314089 TEST=Build and boot Nivviks. Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81676 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09mb/google/*: Drop unused header file console/console.hRuihai Zhou
The header file console/console.h is unused, just drop it. TEST=abuild -t google/corsola -b wugtrio -a TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/81685 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-04-08mb/google/brox: Update verb table to fix headset detectionPoornima Tom
Correct verbtable value for pin widget 20 of Realtek ALC256 based on the updated verbtable received from Realtek. Updated Version : 5.0.3.1. This fixes the headset detection failure, when power_save is enabled in legacy hda driver. BUG=b:330433089 BRANCH=None TEST=Verified headset on Brox When connected to audiojack in power_save state of legacy hda driver, headset is detected and audio is resumed. Change-Id: I71b7d59b3ab5310a0b6cdb31fb5033f94263d151 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81654 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Terry Cheong <htcheong@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-08mb/google/brya: Sort Kconfig option alphabeticallyVarshit Pandya
Change-Id: I878c14058e1edc0f64e37c2fc16b8dcf75b90192 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81631 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-04-04mb/google/screebo: Add FW_CONFIG and device for VPUJamie Ryu
BUG=b:332488817 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared Change-Id: I6d7b35dbf8ac9b0abb42f64a947b4bb94f3c6b0f Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Daniel Kang <daniel.h.kang@intel.com>
2024-04-04mb/google/nissa/variant/sundance: Update devicetree settingsLeo Chou
Based on schematic and gpio table of sundance, generate overridetree.cb settings for sundance. BUG=b:328505938 TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage Change-Id: I857be7bc7f98281cac57fef85bf9f3cef2ec14e9 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-04mb/google/nissa/var/gothrax: Add touchscreen driver for ILI2901A-A210Yunlong Jia
I2C slave addresses 0x41. BUG=b:332458912 BRANCH=None TEST=emerge-nissa coreboot & working correctly in DUT Change-Id: I2d26bfd4f415aa128b6256f83bc58987b15a557a Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81610 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04mb/google/brya/var/xol: Reduce power limits according to battery statusSeunghwan Kim
When battery level is below critical level or battery is not present, cpus need to run with a power optimized configuration to avoid platform instabilities such as system power down. This will check the current battery status and configure cpu power limits using current PD power value. BUG=b:328729536 BRANCH=brya TEST=built and verified MSR PL2/PL4 values. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) [When connected 60W adapter without battery] Before: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 After: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:60000000 [When connected 45W adapter without battery] Before: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 After: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:45000000 constraint_2_power_limit_uw:45000000 Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81614 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-04mb/google/nissa/var/anraggar: Set EN_SPK_PA to low to avoid noiseJianeng Ceng
In order to avoid the noise caused by the codec output to the audio jack during the shutdown and poweron process, we will use GPP_A11 for the codec power supply gate, keep low during the startup process, and wait for the driver to turn on. This change does not affect the beep output of depthcharge. BUG=None TEST=There is no squeaking sound when turning on and off Change-Id: I5982be5a8d965086b46861f4c2c758d9bdee6e75 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81629 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-03mb/google/corsola: Add new board variant WugtrioYang Wu
Add a new Staryu follower device 'Wugtrio'. And also enables SD card support and MIPI panel support. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81585 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03mb/google/corsola: Move MIPI panel selection to BOARD_SPECIFIC_OPTIONS sectionYang Wu
Move starmie mipi panel selection from BOARD_GOOGLE_STARYU_COMMON section to BOARD_SPECIFIC_OPTIONS section. BUG=None TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: Ib5792542f55a78c0840b6169b5ecf092e7cefe98 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81602 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-04-02mb/google/brox: Enable PMC pins to work with PDAshish Kumar Mishra
Enable SMLINK1 interface for PMC-PD communication to configure Type-C muxes. Refer RPL EDS vol 1: 765585. BUG=b:327622474 BRANCH=None TEST=Boot image on SKU2 and check PMC-PD working. Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.com>
2024-04-02mb/google/brya: Make get_soc_power_limit_config() a public functionSeunghwan Kim
Make get_soc_power_limit_config() a public function to use on brya variants. Add prefix 'variant_' for it. BUG=None BRANCH=brya TEST=emerge-brya coreboot Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81616 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-02mb/google/nissa/var/sundance: Generate SPD ID for 4 supported memory partsLeo Chou
Add sundance supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE BUG=b:332201349 TEST=Use part_id_gen to generate related settings Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81612 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 12:46:13 +0000