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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Add VBT file, and override use via Kconfig since all Reef variants
use the same VBT file.
VBT extracted from firmware in ChromeOS recovery image.
Test: built/boot google/reef w/FSP display init
Change-Id: I31156ec7371c0443719fdd9ddac6ed4960c83767
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Base on the grunt board schematic, gpio70 is an alternative way for wlan rst.
Add hook for variants to override default state.
BUG=b:154357210,b:154848243
BRANCH=master
TEST=emerge-grunt coreboot
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Change-Id: Ic3f1c016357dd5090e6adedf96e7593abff29a0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Certain boards require SeaBIOS' HARDWARE_IRQ option to be
deselected in order for the platform to boot. Add a Kconfig
to allow selection of HARDWARE_IRQ enablement, and write to
SeaBIOS' .config file in cases where it needs to be disabled.
Deselect the option for google/rambi variants so they boot
with boards defaults.
Test: build/boot google/clapper, verify board boots vs hanging
at boot menu prompt.
Change-Id: I23e9b30d2d1042c86bd10f134d6fe361edaf8cb2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add a FMAP which supports SMMSTORE and non-ChromeOS payloads,
since Apollo Lake-based devices like Reef cannot use an
automatically-generated FMAP due to strict layout requirements.
Change-Id: If570f92f4f81c0e29777c87756fc5e45af549064
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community
zero.
TEST=Build coreboot, flash, boot to
and log into kernel, execute "wp enable" in console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.
Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence.
BUG=b:155248677
TEST=Boot into OS and check BT is functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update USB3 ports configuration as schematics design.
BUG=b:155026295
TEST=Boot into OS and check WWAN device detected by lsusb.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Separate specific setting to variant from baseboard.
baseboard/romstage.c in current release is only utilized by
careena, we could remove it from the rest of variant build.
BUG=b:154357210,b:154848243
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I658526e44aadc47bdc5538f506a1bfe2e5f20f63
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.
Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.
BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Enable Goodix touch screen and ensure it works properly.
BUG=b:154191288
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the Goodix touch screen function.
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: I236ac56dd0a1817092151bae93e699115ba88e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40598
Reviewed-by: Alex Levin <levinale@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds psys_pmax calculation. There are two types of power
sources. One is barrel jack and the other is USB TYPE-C. The voltage
level is fixed for a barrel jack while TYPE-C may vary depending
on power ratings. We need to get voltage information from
EC and calculate correct psys_pmax value. The psys_pmax needs to be
set before FSP-S since FSP-S will handle the setting passing to pcode,
so move the routine ahead to variant_ramstage_init.
BUG=b:151972149
TEST=emerge-puff coreboot chromeos-bootimage
check firmware log and ensure psys_pmax is passed to FSP
check the data from dump_intel_rapl_consumption in the OS and
ensure the power data is close to an external power meter.
Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Support USB Chicony user facing camera.
BUG=b:155109736
BRANCH=None
TEST=Build and Boot waddledoo board and able to capture image
using user facing camera.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I7580a58086977e239dca49c1def4f03583831662
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The stuffed resistor straps are weaker compared to the internal pull-up.
This can cause the GPIO to read '1' always. Remove the internal pull-up.
Also read the GPIO only on the boards where the board version is
populated.
BUG=b:154301008
TEST=Build and boot the mainboard.
Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update DPTF settings for smooth fan speed control.
BRANCH=firmware-hatch-12672.B
BUG=b:154074920
TEST=Built and test on Helios system
Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=None
BRANCH=None
TEST=Build and Boot waddledoo board and able to capture image
using world facing camera.
Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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1. Add support as per the schematics
2. Add 2 Ports and 2 Endpoints
3. Add support for OTVI8856 and OTVI5676
4. Add ON and OFF logic as Power Rails are same for both sensor
BUG=None
BRANCH=None
TEST=Build and Boot waddledoo board and able to capture image
using world facing camera.
Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add initial support for wheelie variant board.
BUG=b:154664137
BRANCH=None
TEST=build
Change-Id: Id638e987f45c247dae824f221a38ccf32626572f
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update usb2 port strength parameter for usb2_port[0] to improve SI.
BUG=b:154668734
BRANCH=firmware-hatch-12672.B
TEST=Built and checked SI margin of USB2 ports
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:152893285
BRANCH=none
TEST=Build and boot to OS volteer with Intel SATA and reboot
from OS console
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Create the trondo variant of the volteer reference board by copying the
template files to a new directory named for the variant.
BUG=b:154678884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TRONDO
Change-Id: Ie4f9bfe4798e14f91c6cb439f5c5ab2b9ea52b51
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40686
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on USB SI report to fine tune the strength for USB2 port0.
BRANCH=none
BUG=b:153590143
TEST=build and test USB2 port0 function works fine.
Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Include TCSS RTD3 into ACPI DSDT table.
BUG=b:140290596
TEST=Booted to kernel and verified tcss xhci/pcierp/dma
power state D3 entry/exit.
Change-Id: Iae31a29eb23f7370737d097dd401f4056b8b7052
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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SKUID:
49 - Garfour EVT (touch, TypeA DB)
50 - Garfour EVT (non-touch, HDMI DB)
BUG=b:152861752
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I656a2bb2404efded6da6697664748b6c8d2ca4e0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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Since `commit 0ee9b14c09c` the SPD array is set to NULL if no
DIMM is present. This causes failure due to an unconditional use
of `blk.spd_array[i]`, : i={0,1}.
This validates the spd_array is non-NULL before use otherwise it
sets the DIMM as not present.
Puff fails boot with the following log:
```
...
SPD: banks 16, ranks 2, rows 16, columns 10, density 8192 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 16384 MB (per channel)
ASSERTION ERROR: file 'src/soc/intel/cannonlake/cnl_memcfg_init.c', line 47
```
BUG=b:155220125
BRANCH=none
TEST=none
Change-Id: I5f47c849344951d53fa8c67e779b7c46d632d124
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40820
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting the default values for GPIO community power management, causes
issues in detecting TPM interrupts. So to avoid that GPIO PM has to be
disabled in devicetree. But for S0ix it is needed. This patch implements
a workaround in ASL code to enable GPIO PM on S0ix entry and disable it
on S0ix exit.
This patch adds the following three platform specific methods.
1. MS0X to enable power management features for GPIO communities on
entry and on exit, it disables them.
2. MPTS to enable power management features for GPIO communities when
preparing to sleep.
3. MWAK to disable power management features for GPIO communities on
waking up.
BUG=b:148892882
BRANCH=none
TEST="Boot with this change on volteer proto1 and check for GPIO
community config with debugger"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40261
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Moves mipi_camera.asl from mb/google/volteer/acpi/ to
mb/google/volteer/variant/baseboard/include/baseboard/acpi/.
Adds mipi_camera.asl to variant/[volteer|ripto]/include/acpi/.
Adds new VARIANT_HAS_MIPI_CAMERA Kconfig option.
Adds VARIANT_HAS_MIPI_CAMERA for volteer and ripto variants.
BUG=b:154648941, b:154646959
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Ripto and Volteer to kernel.
Change-Id: I2f28243dfb945857d26f27f07968a15a3eeb7a4f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40578
Reviewed-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implements mainboard_get_dram_part_num() to override dram part number
with a part number read from CBI.
BUG=b:146464098
TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer, boot
and log into kernel, execute "mosys memory spd print id" and verify that
the memory part number from the cbi gets displayed properly.
Change-Id: I3a20691f601cb513ee0936c8d141233c3d06db3d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.
Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This is missing configuration of Wiloc projects.
Following Wilco projects configuration. CB:32436
The power architecture on this platform is different than most of our
other x86 devices and needs some special handling to ensure it powers
up again after an EC reset.
BUG=b:150165131
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, Deltaur’s I2C speed has not been tuned yet, so slow down
the H1 I2C to avoid I2C error for short term.
Error logs:
Reading cr50 TPM mode
I2C receive timeout
I2C read failed: bus 3 addr 0x50
BUG=b:154310066
TEST=Check H1 has no I2C error occurring and can be updated by gsctool.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By default, the ACPI status method _STA returns false for the PS/2
keyboard and mouse device of the Wilco EC, so the OS does not enable it.
Enable these devices, by defining the macro SIO_EC_ENABLE_PS2K.
BUG=b:154790509
TEST=Check Keyboard is functional under OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I31c74ddb3608589e5a4753c7e487f250b112bb1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40745
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a FMAP which supports SMMSTORE and non-ChromeOS payloads,
since GeminiLake-based devices like Octopus cannot use an
automatically-generated FMAP due to strict layout requirements.
Change-Id: Iebacbea5b3a782b2abf1d6e28acd21b87dc9402b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40596
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add VBT file, extracted from stock Google firmware, and
select its use via Kconfig.
Change-Id: I256c1c72d1d1e40ea9426fa717bfc4f9c950a91f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Cirque touchpad uses I2C_HID driver.
BUG=b:152931802
TEST=Touch pad can work well in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3f8d5abad2f153f395ba7e3f979ad3d2526e040c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Chip drivers not overrided if out of domain. Only device can get
override, so move the code under domain.
BUG=b:152924290,b:152931802
TEST=Touch screen and Touch pad can work well.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iaaa73e36ec268d26ebd3cafab79179fe22a926a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The change applies the DPTF parameters received from the thermal team.
1. Set PL1 Min to 3W
2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec
3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points
for tablet mode.
4. Update trigger points of CPU/TSR0/TSR1
BUG=b:154564062, b:154290855
BRANCH=hatch
TEST=build and verified by thermal team.
Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:149588766
TEST=ELAN and Goodix touchscreen works.
Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I1c3e75eb03a8ab434ee58bf36a155f2255612083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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If set variant early gpio table NULL, it will override the baseboard
table. Move early gpio table to variant level.
BUG=b:154310066
TEST=Check H1 has no I2C error occurs.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie4c4648ccf918446a499019a4f77f64e43a92c76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Tuning i2c frequency for jinlon:
I2C0: 392.7 KHz
I2C1: 390 KHz
I2C3: unused
I2C4: 388.8 KHz
BUG=b:154900217
BRANCH=hatch
TEST=emerge-hatch coreboot chromeos-bootimage, and measured with
scope
Change-Id: I9b186193f34027d03dd349cf1e29bb266b167383
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1) Allows MKBP events from the EC to wake the system from suspend states.
2) Remove EC_HOST_EVENT_MKBP from the EC_SCI_EVENTS mask, so that MKBP
events don't generate an SCI. The EC is also being changed to use host
events to wake up the system, and use the EC_INT_L line for MKBP IRQ
signalling. Otherwise, there would be two IRQs generated for MKBP events.
BUG=b:148976961
BRANCH=firmware-hatch-12672.B
TEST=Verify MKBP events wake system
TEST=Verify MKBP IRQs are run
Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:154071868
BRANCH=none
TEST=builds
Change-Id: I9c602476a80a97438af01e3c48fac385532373a4
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Copy over DPTF parameters from Puff.
BUG=b:153589525
BRANCH=none
TEST=none
Change-Id: Ic619826205be06f30055fbbc537f3d302dd039bd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40423
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copy over DPTF parameters from Puff.
BUG=b:153589525
BRANCH=none
TEST=none
Change-Id: I7270db1283a9c0ee4746da038020e432aeb6dc5e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40422
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The device is always there, the Chromium OS configs always enable it,
so let's mirror that here for a better out of the box experience.
Change-Id: Ia2073ee7ecbdb37473e1f1002bc9ae0f7df58e42
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40657
Reviewed-by: Michael Niewöhner
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The device is always there, the Chromium OS config always enables it,
so let's mirror that here for a better out of the box experience.
Change-Id: Ic43a314aaed635ae2943df02abc5d163cc3c4ffd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40658
Reviewed-by: Michael Niewöhner
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5bb1a819475383719dbda32d9b5fea63da1e6713
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Switch USB2 port1 and port3 for duffy and kaisa due to circuit change.
BUG=b:153682207, b:154451230, b:154445635
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
boot on puff board
Change-Id: I9c0cbcbefd045085fb70cf4f41869ab9b98103c4
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the
appropriate calling stage (bootblock or romstage). This means that
ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE
are 1. This keeps tripping up people who are just trying to write a
simple "are we in verstage (i.e. wherever the vboot init logic runs)"
check, e.g. for TPM init functions which may run in "verstage" or
ramstage depending on whether vboot is enabled. Those checks will not
work as intended for CONFIG_SEPARATE_VERSTAGE=n.
This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to
clarify that this macro can really only be used to check whether code is
running in a *separate* verstage, and clue people in that they may need
to cover the linked-in verstage case as well.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Romstage is now where software sync is performed for chromebooks.
EFS2 has been ported to romstage from Depthcharge. Puff should
follow.
This patch enables CONFIG_EARLY_EC_SYNC and disables
CONFIG_VBOOT_EC_EFS. EFS2 will be done in romstage.
BUG=b:147298634, chromium:1045217
BRANCH=none
TEST=Verify software sync succeeds on Puff.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I8d7c25f8281496c7adb282f5d4e0fc192d746e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40390
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EDID and command sequence are from BOE, the vendor.
BUG=b:148997748
TEST=Boots on Chromebook Kakadu and displayed developer firmware screen successfully.
Change-Id: Ieb510cb28882afc5b8023c2a57b31187e4a09fbd
Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40396
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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USB routing has changed on reference schematics after Puff rev1 has
built. This may confuse people trying to c&p devicetree from the Puff.
So add comment to clearly note that there was change, hopefully
preventing c&p errors.
BUG=b:153682207
BRANCH=None
TEST=None
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I5c43a5c04c81b6708c9eeabc48ef11961d7c8561
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40546
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
SMBus uses 7-bits address, change it from 8-bits to 7-bits.
BUG=b:151702387
TEST=Check Memory SPD data is correct in console log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Deltan will be using the integrated Intel GbE for LAN
functionality. Deltaur will not have a LAN port, and so does not need
the GbE region. This patch adds a new FMAP descriptor file which
explicitly supports the GbE region (chromeos-gbe.fmd), and removes the
GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd,
and Deltaur is assigned chromeos.fmd.
BUG=b:150165131
TEST=emerge-deltaur coreboot chromeos-bootimage
and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The WDB (Write Data Buffer) is a data region in CAR, used as a
scratchpad in the read and write training algorithms of memory
initialization. Both SNB and IVB use this buffer, but HSW does not.
Unlike earlier chipsets, Haswell contains much more in-hardware memory
training machinery, known as REUT (Robust Electrical Unified Testing).
Among other changes, the REUT hardware has a pattern storage buffer,
which renders the need for a pattern storage buffer in CAR obsolete.
Deprecate the WDB-related parameters in the pei_data structure for
Haswell, as they are leftovers from the previous generation's MRC.
Remove them from the mainboards, and explain why they are not required.
Because the MRC ABI has to remain the same, the layout of pei_data must
not be changed, so rename the WDB parameters instead of deleting them.
Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf.
Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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Each physical port should have the same group and position for both USB2
and USB3, but puff and its variants use different layout than the
baseboard so they must override PLD.
Ports are split into two groups for front and back, with positions in
each group numbered from left to right.
BUG=b:151579409
BRANCH=none
TEST=PLD_GroupToken and PLD_GroupPosition are set as expected in SSDT.
Change-Id: Ibe19e4faa1fbc7117687d789e9bd5584852a48c0
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
There have been two cases of incompatibilities between overlapping
changes, and they need to be resolved in a single commit to unbreak the
tree:
1. CB:40389 introduced a new use of write_secdata while CB:40359 removed
that function in favor of safe_write.
Follow the refactor of the latter in the code introduced by the former.
2. CB:39849 changed google_chromeec_get_usb_pd_power_info()'s interface
and adapted all its users. Except for duffy and kaisa which were only
added in CB:40223 and CB:40393 respectively, so reapply the patch to
puff's mainboard.c to their mainboard.c files.
Change-Id: Ib8dfcd61bb79e0a487eaa60e719bd93561f2d97a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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This patch adds psys_pmax calculation. There are two types of power
sources. One is barrel jack and the other is USB TYPE-C. The voltage
level is fixed for a barrel jack while TYPE-C may vary depending
on power ratings. We need to get voltage information from
EC and calculate correct psys_pmax value. The psys_pmax needs to be
set before FSP-S since FSP-S will handle the setting passing to pcode,
so move the routine ahead to variant_ramstage_init.
BUG=b:151972149
TEST=emerge-puff coreboot chromeos-bootimage
check firmware log and ensure psys_pmax is passed to FSP
check the data from dump_intel_rapl_consumption in the OS and
ensure the power data is close to an external power meter.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8ea01f856411e05a533489280fc2b4a46a1440c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Update memory topology for spd info. Deltan supports SODIMM and
Deltaur supports MEMORYDOWN.
BUG=b:151702387
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If314894325d6f222807030a36f8c4cefecfe5bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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This patch adds voltage and curent parameters in
google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could
use the voltage and current information to calculate charger power rating.
The reason for this change is, some applications need the voltage information
to calculate correct system power eg PsysPmax.
BUG=b:151972149
TEST=emerge-puff coreboot; emerge-fizz coreboot
Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
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Remove explicit setting of iDisp Link parameters. These settings are
related to configuration for the link between HD-Audio controller and
Display unit for purposes of HDMI/DP Audio playback. During PO,
observed that without setting these params display part was not
binding. With the latest code verified that we dont need to explicitly
set these parameters anymore. HDMI/DP audio playback works fine with
default settings.
BUG=b:151451125
BRANCH:none
TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jairaj Arava <jairaj.arava@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7.
Previous setting was wrong so correct it.
BUG=b:150165131
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:154279851
TEST=none
Change-Id: Ibb56d97d5180ab199c52119135f7eff265908667
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:154178408 b:154293730
BRANCH=None
TEST=build waddledoo successful and Linux has no TPM IRQ timeout error.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Configure DRAM population strap GPIO according to the schematics.
Configure an internal pull-up to support the boards in which the strap
is not populated. Read the strap and pass that information to FSP for
memory initialization.
BUG=b:152275658, b:154301008
TEST=Build and boot the mainboard. Ensure that the strap information is
read as expected and passed to FSP.
Change-Id: I69583f35ffc219bae9ce06bd4ba9898ed0d4d21d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39812
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update device enable/disable based on PCH EDS#576591 vol1 rev1.2
BRANCH=none
BUG=b:154037185
TEST= boot up OS in volteer and check and check lspci
Unsupported IP should be visable from lspci result
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I61a328da1014ab7584c3ec789971a106c7a0a403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40394
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The samsung-K4U6E3S4AA-MGCL.spd.hex is not used and planed by anyone
yet. On the other hand, the spd content is not correct based on JSL
spec as well.
BUG=b:153426401
TEST=build waddledoo and waddledee successfully.
Change-Id: If71e3ef2e3385378633549bf8709a1cd6ecc0dd3
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Reference Arcada to add device tree for Cirque touchpad.
BUG=b:152931802
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia354702c8054b5826d45896f7bff268335726028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Modify stop_delay as 115ms to waiting for Melfas device I2C interface
ready after touch fw auto update and rebind driver.
BUG=b:153708773
BRANCH=drallion
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ib392190d2b4188ee228d8ca4873e03176d2f127f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40357
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Override VBT to fix CRC error issue with psr2 panel for kled.
Cq-Depend: chrome-internal:2877637
BUG=b:145963505
BRANCH=hatch
TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage
Change-Id: If201d449e910f80dc514c142aec4808a44fa31a9
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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A verbatim copy of variants/puff
V.2: rebased on duffy.
BUG=b:152951180
BRANCH=none
TEST=none
Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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A verbatim copy of variants/puff.
BUG=b:152951181
BRANCH=none
TEST=none
Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:152927525
BRANCH=none
TEST=builds
Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Tunes the headphone amp i2c with measured signal shape.
BUG=b:147192377
BRANCH=none
TEST=builds and measured i2c frequency below 400khz
Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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We decided to add a third RAM_CODE pin to the Trogdor family for devices
after rev1. This patch adds support to read it. Since the newly used pin
was previously unconnected (not pulled down) on rev1, this will change
the RAM_CODE result for previous versions (and actually make it
undetermined until we enable tri-state). But since we're not actually
using RAM_CODE for anything yet, and since those are development
revisions that will eventually be discontinued, this should be fine.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
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Update tdp_pl1_override value to 15W for CML-U based nightfury platform.
BUG=None
BRANCH=firmware-hatch-12672.B
TEST=Built
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Reference Drallion to add device tree for Melfas touch screen.
BUG=b:152924290
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.
BRANCH=octopus
BUG=b:153782196
TEST=Verified usb operation successfully.
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ELAN EKTH6918 USI touchscreen support.
BUG=b:152936745
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Add SiS9813 USI touchscreen support.
BUG=b:152936541
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I38d429245810f64a03253b5076391af843f8d0de
Fixes: e2ac5b7a36 ("mb/google/hatch/variants: Add DPTF based Fan control")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39
Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to Intel Document #616599,
1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10
columns)
2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel
x16)
This change fixes those two values in the existing SPD files for
Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a
generic SPD).
BUG=b:152827558
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
Volteer to kernel.
Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community
zero instead of community 1.
BUG=b:152876091
TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to
and log into Volteer kernel, execute "wp enable" in H1 console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in H1 console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.
Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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- Configure devicetree for enabling GbE on variant
and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.
BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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For Deltaur and Deltan variants return proper SKU ID based on EC
firmware type and sensor detect GPIO value
BUG=b:152544516
TEST=make build successful for deltan
Change-Id: I20a497739e5062400b093648c3a634203dec6105
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update memory configuration on Tiger Lake platform to enable Early
Command Training. This feature was not supported before FSP v2527.
BUG=b:150357377
BRANCH=None
TEST= Build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When EC_GOOGLE_CHROMEEC_SKUID is selected provide an
implementation of smbios_mainboard_manufacturer() so the code
doesn't need to be duplicated in the mainboards.
BUG=b:153767369
Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Modify board name from "Kadadu" to "Kakadu"
BUG=b:153590144
TEST=CPU log show "Starting depthcharge on Kakadu..."
BRANCH=kukui
Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Build and boot the mainboard. Ensure that the touchpad is
operational.
Change-Id: I937462cd3992a884194bbd1759a0802a147e925a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up
of 20K. Retain it during the GPIO pad configuration.
BUG=b:150985246
TEST=Boot the mainboard.
Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In some cases Hatch variants are not laptop form-factors such
as Puff. Ensure that the base configuration does not assume
the form factor and allow variants to elect their intended
use-case.
Note that the issue is that early ec sync needs to be
disabled for EFS2 to function correctly, see commit 6daa8c3ba5f
from the FIXME line. The relationship is that desktops do not
have a battery.
BUG=b:152951181
BRANCH=none
TEST=none
Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40252
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apply initial DPTF parameters for nightfury from internal thermal team. Will update after further thermal/performance tuning.
BUG=b:149226871
BRANCH=firmware-hatch-12672.B
TEST=built and verified FAN worked by DPTF active policy
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I712bdd8edc999ef7ee33f4adf21893be12e86bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.
BRANCH=octopus
BUG=b:149723583
TEST=Verified USB operation successfully.
Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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