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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-04-17 19:32:33 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-04-20 06:37:32 +0000
commita48e7111209f7257cf40b317dc4df42e7c13ae24 (patch)
tree3f53658ce95ea9a88bb10fad35e9a1d1d7a99d29 /src/mainboard/google
parent9a3486e018f7ae54563d8be2c11297542e786597 (diff)
mb/google/deltaur: Correct H1 I2C gpio pin setting
H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7. Previous setting was wrong so correct it. BUG=b:150165131 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/gpio.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c
index 46a5cdd79d..71a07b6d46 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c
+++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c
@@ -303,14 +303,14 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
/* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
- /* H6 : GPP_H6 ==> SPK_DET1 */
- PAD_CFG_GPI(GPP_H6, NONE, PLTRST),
- /* H7 : GPP_H7 ==> NC */
- PAD_NC(GPP_H7, NONE),
- /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */
- PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
- /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */
- PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+ /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* H8 : GPP_H8 ==> NC */
+ PAD_NC(GPP_H8, NONE),
+ /* H9 : GPP_H9 ==> NC */
+ PAD_NC(GPP_H9, NONE),
/* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
/* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */
@@ -436,10 +436,10 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
/* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
- /* H8 : GPP_H8 ==> I2C_SDA_PCH_H1 */
- PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
- /* H9 : GPP_H9 ==> I2C_SCL_PCH_H1 */
- PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+ /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* GPD3: GPD3 ==> SIO_PWRBTN# */
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
};