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2023-03-15mb/google/brya/var/omnigul: Correct mux_conn for USB C1Dtrain Hsu
Modify USB C1 mux_conn to 1. It should match ec settings. BUG=b:272394875, b:272667290 BRANCH=firmware-brya-14505.B TEST=Plug USB-C hub in USB C1 and could recognize USB drive and hdmi. Change-Id: I61b77405d1790b044174cef954e5bf910141f424 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15mb/google/brya/var/omnigul:Fixed can't detect 3.5mm headphone jackJamie Chen
1. Modify irq_gpio GPP_H0 -> GPP_A23 BUG=b:272218750 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8e178b149015ed8027b547e4c2109b3aef8a7484 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15mb/google/brya/var/omnigul:Fixed Touch screen has no actionJamie Chen
1. Add generic.stop_gpio = GPP_C6 2. Add c.stop_off_delay_ms = 2 BUG=b:271966059 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I33857443d8a68e7b50ac5f8f08afc017fe4f5a59 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-14mb/google/skyrim/var/frostflow: Update the STT settingsFrank Wu
According to file thermal_table_0310, adjust the STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Change-Id: If4500c85dcea051aca15602f1fb4b5ec80b73e67 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-03-14mb/google/dedede/var/dibbi: Configure I2C times for audioAmanda Huang
Configure the I2C bus high and low time for audio. BUG=b:271804915 BRANCH=dedede TEST=Build and confirm I2C clock for audio is between 380 kHz and 400 kHz Change-Id: I2987a39abc5527844424edfa1cf70d5c5cea5357 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-03-14mb/google/brya: Create uldren variantvan_chen
Create the uldren variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:271513530 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ULDREN Change-Id: Ibbcd34fb4ef1f7464f0c94d2fcf75280c3eed6be Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73680 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13mb/google/skyrim/var/winterhold: Change touch controller T3EricKY Cheng
Change stop_delay_ms time(T3) from 180 to 150 to meet specification. T3 min-value of HID-I2C should be 150ms. BUG=b:267280863 TEST=emerge-skyrim coreboot chromeos-bootimage. Change-Id: I7ef7db4edaecece1fa5ab07e30a80e556ed35f8b Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-13mb/google/brask/var/kinox: Allow USB2/3 hotplug to wakeup S0ixDtrain Hsu
Allow USB2/3 hotplug event to wake up S0ix. BUG=b:236189998 BRANCH=firmware-brya-14505.B TEST=Verify USB-A device could wake up Kinox Change-Id: I8aeeeac6c21289b70bdc7ffddc57687ac39e8456 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-10mb/google/skyrim/var/markarth: Add 2 Micron parts to RAM ID tableJohn Su
Add new ram_id:0011 for Micron MT62F1G32D2DS-023 WT:B. Add new ram_id:0100 for Micron MT62F2G32D4DS-023 WT:B. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) MT62F1G32D2DS-023 WT:B 3 (0011) H58G66BK8BX067 4 (0100) MT62F2G32D4DS-023 WT:B 4 (0100) BUG=b:271188237 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I59a6a6dff249cd4fe982a4de824848f1bac0ecba Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73510 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mb/google/brya/var/omnigul: Fix SSD can not boot into OSJamie Chen
1. device ref pcie_rp11 -> pcie_rp9 on. BUG=b:270657362 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: If23785f42466ba94f33d4d15dde96de29dbb3a1e Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73530 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mb/google/brya/var/omnigul: Enable ELAN touchscreenDtrain Hsu
Enable ELAN eKTH5015M touchscreen. BUG=b:271966059 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I41eac949f21a48098b445f8d1b05f308672f7ab8 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10Revert "mb/google/skyrim: Create whiterun variant"Jon Murphy
For simplicity, OEM devices are given a single codename per build variant. Winterhold was intended to be the lead device and was chosen as the code name for this OEM. Unfortunately, Winterhold was cancelled. We attempted to rename Winterhold to Whiterun to avoid future confusion. Again, unfortunately, since some devices were already built, changing the name requires a manual change to force the firmware to be taken by the DUT. This was not a reasonable path forward, so we're abandoning the naming to Whiterun. This reverts commit af69de494e2c32140ce5e00a1562c2845345b1bf. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idef95f0f4f369b235937e1806ce57c427e441f21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73583 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-09mb/google/guybrush: Store XHCI resourcesRobert Zieba
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. Example elog contents: ``` 250 | 2022-10-11 16:04:49 | S0ix Enter 251 | 2022-10-11 16:04:53 | S0ix Exit 252 | 2022-10-11 16:04:53 | Wake Source | GPE # | 31 253 | 2022-10-11 16:04:53 | Wake Source | PME - XHCI (USB 2.0 port) | 1 254 | 2022-10-11 16:05:24 | S0ix Enter 255 | 2022-10-11 16:05:27 | S0ix Exit 256 | 2022-10-11 16:05:27 | Wake Source | GPE # | 31 257 | 2022-10-11 16:05:27 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin, verified that XHCI wake events show up in elog Change-Id: I1d0911df9e3102791bf7b5723ac38e2ba82a9db6 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68326 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/google/skyrim: Store XHCI PCI resourcessRobert Zieba
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. Example elog contents: ``` 244 | 2022-10-11 15:49:24 | S0ix Enter 245 | 2022-10-11 15:49:29 | S0ix Exit 246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31 247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256 248 | 2022-10-11 15:50:08 | S0ix Enter 249 | 2022-10-11 15:50:16 | S0ix Exit 250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31 251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BUG=b:186792595 TEST=Ran on skyrim proto, verified that wake events show in elog Change-Id: I529f541a8932267a8825773ddc582beafb27da63 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68325 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/google/skyrim: override winterhold PCIe configMartin Roth
Winterhold boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09mb/google/skyrim: drop link_hotplug from port descriptorsMatt DeVillier
These ports are not hot pluggable, so drop the parameter, which will result it in being set to zero / not enabled. BUG=none TEST=build boot skyrim, verify all PCIe devices functional. BRANCH=skyrim Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Enable L1 ASPM substates for PCIe devicesMatt DeVillier
Enable both L1.1 and L1.2 substates for the WiFi, SD card reader, and SSD (both NVMe and eMMC). If a given device does not support a particular substate, then it will not be enabled during PCIe enumeration by coreboot. BUG=b:270690572 TEST=build/boot multiple skyrim/whiterun/frostflow SKUs with different storage configs, verify WiFi/SD card/SSD all functional and have L1 substates enabled insofar as they are supported by the device. BRANCH=skyrim Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Allow port descriptors to be overriddenMartin Roth
This allows variants to override the skyrim port descriptors. BUG=None TEST=Tested with following patches BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09mb/google/dedede/var/kracko: Generate new SPD ID for new memory partsRobert Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:272173189 TEST=run part_id_gen to generate SPD id Change-Id: I141bda6eda3f658ca608c86ad0b320d018598514 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73554 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/google/brya/var/marasov: Half touch power-on delay to 150 msFrank Chu
Decrease Touch i2c delay during power-on sequence from 300 ms to 150 ms to make S0ix resume time meet requirement. BUG=b:264199989 TEST=Run the following test from chroot. test_that -b {BOARD_NAME} {device IP} f:.*power_UiResume/control Check seconds_system_resume value less than 500 msec Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ib81a9c1a90589b8b08e6ce6471db2abef96047ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/73532 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08mb/google/skyrim: Enable SPL fusing on whiterun/winterholdMartin Roth
Enable whiterun/winterhold platforms to send the fuse SPL (security patch level) command to the PSP. BUG=b:254568112 TEST=On a platform that supports SPL fusing, a message indicating that fusing was requested will appear in the coreboot console log, followed by a puff of smoke when the fuse is set and the message "OK" again on the debug console. (Kidding about the smoke.) BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I45578597234ba672c89ac421b4626088faca27d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72914 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-08mb/google/rex: Rename touchscreen signals as per latest Rex schematicsEran Mitrani
Touchscreen signals were renamed for Rex schematics dated 21st Dec'22. This CL fixes the comments for those signals. BUG=b:263411413 TEST=None required (changed comments only) Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08mb/google/brask/var/constitution: update gpio settingsMorris Hsu
Remove GPP_D11,GPP_D12 in ramstage, follow baseboard brask setting. TEST=emerge-brask coreboot make sure HDMIA can display Change-Id: I953170f006699e3dc9d6111ded8234f66b9162c7 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-08mb/{brya,hdaes}/include/ec: Add EC_HOST_EVENT_GPUTarun Tuli
EC_HOST_EVENT_GPU was renamed from EC_HOST_EVENT_USB_CHARGER and thought to no longer be used. It was subsequently removed in I9e3e0e9b45385766343489ae2d8fc43fb0954923 Add back the mask for this event as it is infact required on certain Brya (Agah) and Hades variants. Signed-off-by: Tarun Tuli <taruntuli@google.com> BUG=b:216485035,b:258126464,b:266631157 BRANCH=none TEST=D-notifier events are received again from EC Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73217 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-08mb/google/nissa/var/craask: Extend sd_hold for touchpad/touchscreenTyler Wang
Extend sd_hold to meet touchpad/touchscreen SPEC. touchscreen: tHD > 100 ns touchpad: 900 ns > tHD > 300 ns After applied the change, the tHD meets reqirement. touchscreen: 35 ns --> 260 ns touchpad: 43 ns --> 368 ns BUG=b:271524470 TEST=build and measure the timing meet SPEC Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iec2f72da80ffe8d4dd494caabbe1a97e52a81e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-03-07mb/google/hades: Change memory to SODIMMEric Lai
Add SODIMM support, drop the solderdown based on schematics. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85ec79c3d8f1147a875c4d04017bb50347121ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-07mb/google/geralt: Set +-5.7V to TPS65132s EEPROMyangcong
It is necessary to increase the AVDD/AVEE of TPS65132s PMIC to +-5.7V for powering on BOE_TV110C9M_LL0. So we set the default value to +-5.7V and program the value to the EEPROM when configuring the display at the first time. In this way, TPS65132s could load the correct setting from the EEPROM after booting into kernel. BUG=b:268292556 TEST=test firmware display pass and AVDD/AVEE is +-5.7V on Geralt. Change-Id: I29236818444cac84d42386a371cd8934048ff948 Signed-off-by: yangcong <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73443 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-03-07mb/google/skyrim: Move SPL setting to variantsChris Wang
Move the sustained_power_limit_mW setting from the baseboard to variants. This setting will be needed before STT is enabled, but once STT is enabled, this setting should be removed. BUG=b:265267957 BRANCH=none TEST=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I7b9779600cfa8c7581732e936a714728fd618d20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-07mb/google/brya/var/taeko: Enable Fast VMode for taekoJoey Peng
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I82c2016d9dfb39ff7b372815737d4ae62875340c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73373 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-07mb/google/brya/var/taeko: use RPL FSP headersJoey Peng
To support an RPL SKU on taeko, taeko must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for taeko so that it will use the RPL FSP headers for taeko. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot taeko to kernel. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Cq-Depend: chrome-internal:5544049, chromium:4302529 Change-Id: Ic97400555dabb237325e7c4a8d5edcbb4779cdb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-05mb/google/skyrim: Disable cardbus supportMartin Roth
Skyrim does not have a cardbus socket, so disable it. Maybe cardbus support shouldn't be enabled by default? BUG=None TEST="PC Card (PCMCIA) is supported" no longer shows up in dmidecode output. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05skyrim/overridetree.cb: Remove gpio_keys ACPI nodeTim Van Patten
Only Frostflow supports the stylus, so remove the gpio-keys ACPI node from Skyrim. The Kconfig value DRIVERS_GENERIC_GPIO_KEYS is still enabled for all Skyrim variants, since coreboot will drop the driver from the BIOS image if there are no references to it (in the devicetree). If some other design ends up using the stylus in the future we won't have to bring it back. BUG: none TEST: build_packages --board=skyrim chromeos-bootimage --autosetgov Change-Id: I9ffe215741b72b678d74405769f35167d8ded4b5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-05mb/google/geralt: Add NAU8318 support for GeraltTrevor Wu
Add a config "USE_NAU8318" to enable NAU8318 support. NAU8318 is another speaker used in Geralt. NAU8318 supports beep function via GPIO control. So we configure the GPIO pins and pass them to the payload. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I21009a20809f398de4628ff0c11bcbd0e7591443 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73413 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add MAX98390 support for GeraltTrevor Wu
Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add mtcmos bus protection for displayLiju-Clr Chen
Enable bus protection for display to avoid bus hang and incomplete bus transaction. BUG=b:264204465 TEST=test firmware and kernel display pass for MIPI panel on geralt. Change-Id: Iac61a69f2b84966dd468442daaa59d83eec775aa Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73411 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/hades: Add baseboard device treeEric Lai
Add minimum device tree. Leave IOs default disable to optimize variant override complexity. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-04mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0011 for Hynix H58G56BK8BX068. Add new ram_id:0100 for Hynix H58G66BK8BX067. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) H58G66BK8BX067 4 (0100) BUG=b:270629852 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73252 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-04mb/google/skyrim/var/frostflow: Update DPTC and STT settingsFrank Wu
According to thermal_table_0215, adjust DPTC and STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang
The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-04mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dtScott Chao
BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73174 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04mb/google/brya: remove the skolas baseboardNick Vaccaro
The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-03mb/google/skyrim: Disable USE_SELECTIVE_GOP_INITMartin Roth
This is causing some issues, so disable it until those issues can be resolved. BUG=b:271437658, b:271199389, b:270077971 TEST=Screen always lights up on boot & after S0i3 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-02mb/google/rex: Enable VPURavi Sarawadi
BUG=b:270529665 TEST=Verify the build and boot on Rex board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-02acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `K3KL6L60GM-MGCT`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id0925ccec014c9c535178ed3d908e60889df624d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign H58G56BK7BX068 1 (0001) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9eea7e277628992be9b7768a678a50425444002a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02mb/google/brask/var/constitution: Enable Fast VMode for constitutionMorris Hsu
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I1e68f708b7740567e24f8a3ddb9832aeec7ee6b5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73247 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-01mb/google/brya/acpi: Remove extra DC boost byteTarun Tuli
The DC boost bit was intended to be in the Controller Params word rather than its own byte. Correct this error. BUG=b:214581372 TEST=build Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-28mb/google/kahlee/mainboard: use ACPI_SCI_IRQ definitionFelix Held
Use the ACPI_SCI_IRQ definition instead of a magic value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia860668b5c93b1b8882459d9f983cf3a23d16392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73321 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-27mb/google/skryim: Add RECOVERY_MRC_CACHE FMAP sectionKarthikeyan Ramasubramanian
Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP section to cache the MRC training data in recovery mode. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS directory entry is populated with the appropriate MRC_CACHE FMAP section. Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-27mb/google/skyrim/var/winterhold: Use fw_config to probe FPEricKY Cheng
Use fw_config to probe fingerprint. BUG=b:269986245 TEST=emerge-skyrim coreboot chromeos-bootimage. Test result is pass with 1000 reboot cycles. Change-Id: I4b4bca42dd78dfd5b8636ff3cb05406d2d0c94f7 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-27mb/google/brya/var/osiris: Enable Fast VMode for osirisDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I35f577e1bab0f8dda10061903df13730e2c8ee04 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-27mb/google/brya/var/osiris: use RPL FSP headersDavid Wu
To support an RPL SKU on osiris, osiris must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for osiris so that it will use the RPL FSP headers for osiris. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot osiris to kernel. Cq-Depend: chromium:4290627, chrome-internal:5516851 Change-Id: If8de42a82fd85ffa8b9836e6024f119bc798f4fc Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-27mb/google/nissa/var/xivu: Disable world-facing microphoneIan Feng
Remove world-facing microphone for xivu360. Switching to world-facing camera will use the user-facing microphone to record sound. BUG=b:263927799 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ibb720974b6488ce4453081e0bc5b4e7f34a6b0f6 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-27mb/google/dedede/var/dibbi: Improve USB2 strengthAmanda Huang
BUG=b:269786649 TEST=build and test USB2 port function works fine BRANCH=dedede Change-Id: I63928a0d8ce6b2365250fd96572f4a2db948c19d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-02-27mb/google/brask/var/constitution: use RPL FSP headersMorris Hsu
To support an RPL SKU on constitution, it must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for constitution so that it will use the RPL FSP headers. BUG=b:267539938 TEST=emerge-brask intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: Ie4f5eb6ebb372ad07308ff25c9eb69a83793c656 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73246 Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-27mb/google/brask/var/constitution: Update overridetreeMorris Hsu
Update override devicetree based on schematics. BUG=None TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I883a806950821e6306242975764930035a94888e Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-02-27mb/google/rex: Remove `fixme` from gpio.hKapil Porwal
Remove `fixme` from gpio.h since it has been addressed. BUG=none TEST=Only a cosmetic change Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I79a2493dba6becd4b8c1ebf37e452a5a173eb396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-24mb/google/skyrim/var/winterhold: Remove gpio-keys ACPI node for PENHEricKY Cheng
Remove ACPI node for pen eject event to meet project design. BUG=b:265106657 TEST=emerge-skyrim coreboot chromeos-bootimage Change-Id: I732de49c6319397d93671c48a6518c7c7e955fdc Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73154 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-24mb/google/skyrim/var/crystaldrift: Generate RAM IDs for new memory partsYunlong Jia
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 3 (0011) BUG=b:265190498 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I860f10552e4e4180e09ab805ca82b108fdc8f21a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73049 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24Revert "mb/google/brya/var/gladios: Update gpio table"Robert Chen
This reverts commit 3eb17b91daac0b3acaffb01568d724d23c6f0eea. Reason for revert: PLTRST only keeps 18xms and it's too short for eMMC disk fully reset. Change-Id: If4277cb600bfe4e071959dacaf204fe7d3518f68 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73202 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-24Revert "mb/google/brya/var/lisbon: Update gpio table"Robert Chen
This reverts commit 0e0f9e51c4c4f190cbe7ef5bffa138601c644d3c. Reason for revert: PLTRST only keeps 18xms and it's too short for eMMC disk fully reset. Change-Id: I13b93747bdb4d39de1ffcfdc020648871fa6e048 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73203 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-24mb/google/brask/var/constitution: update gpio settingsMorris Hsu
Update GPP_E12,GPP_E13,GPP_H19 in ramstage. Update GPP_F11 in bootblock. TEST=emerge-brask coreboot Change-Id: Icdca7f574282da140ec64cea9cdda3ebccbe3eb8 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73194 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23mb/google/rex: Set audio GPIOs based on fw_configKapil Porwal
Define some actions based on probe results for audio: - Disable the SoundWire GPIOs when I2S option is selected. - Disable the I2S GPIOs when SoundWire option is selected. - Disable all the GPIOs when no audio is enabled. BUG=b:269497731 TEST=Test that GPIOs are configured based on the current value of the fw_config field in cbi. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0ed452a0d08e6779add318d9bbd1e97b50b6aea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-23mb/google/rex: Use gpio padbased table overrideKapil Porwal
In order to improve gpio merge mechanism. Change iteration override to padbased table override. And the following patch will change fw config override with ramstage gpio table override. Port of commit 7aef2b1294f2 ("mb/google/nissa: Apply gpio padbased table override") BUG=none TEST=Verify devbeep at depthcharge console Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2ee86bbec7d25a35d726f29ad79891f1054bf52c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73182 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-23intel/alderlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-23mb/google/skyrim/var/crystaldrift: Update devicetree settingYunlong Jia
Setup FW_Config for our project. Configure USBHub\PIXA Touchpad\Audio(rt5682s & alc1019). BRANCH=None BUG=b:262798445, b:268621319 TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I2c590ae36d4d089f70e1799189cd414f825e5b8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-22mb/google/*: Resume from suspend on critical batteryIvan Chen
This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate when the state of charge drops to low_battery_shutdown_percent. BUG=b:255465618 TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898) Verify system resumes from s0ix and then enter S5 on nivviks with steps: 1. disconnect AC 2. powerd_dbus_suspend --disable_dark_resume=false 3. fakebatt 5 4. fakebatt 4 Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9 Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-02-22Revert "mb/google/poppy: Nami - invoke power cycle of FPMCU on startup"Subrata Banik
This reverts commit 2e6fa8206e0a3bdd2e53542b6377fe2b37e3f26e. Reason for revert: causing `redefinition` issue. src/mainboard/google/poppy/variants/nami/gpio.c:527:26: error: redefinition of 'variant_romstage_gpio_table' const struct pad_config *variant_romstage_gpio_table(size_t *num) ^ src/mainboard/google/poppy/variants/nami/gpio.c:426:26: note: previous definition is here const struct pad_config *variant_romstage_gpio_table(size_t *num) ^ Change-Id: I107cce8bf3a5bf38edb39b9d46512ee0d467d354 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73210 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-02-22mb/google/dedede/var/dibbi: Enable USB2 port 6Sam McNally
USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the port. BUG=b:269690930 TEST=kernel can detect a PL2303 USB device BRANCH=dedede Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05 Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-22mb/google/poppy: Nami - invoke power cycle of FPMCU on startupTarun Tuli
Add functionality such that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami. Confirmed power is off for 150ms seconds on boot. Confirmed RCC_CSR of FPMCU indicates power cycle occurred. Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-21mb/google/skyrim/var/markarth: Update Elan touchscreen power sequenceJohn Su
Based on product spec v1.4, update T3 timing from 180 ms to 150 ms. BRANCH=none BUG=b:262734395 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-20mb/google/brya/var/skolas: remove disable_package_c_state_demotionNick Vaccaro
Package C state demotion is now disabled for all RPL SoCs from within soc/intel/alderlake/fsp_params, so no need to duplicate that in the skolas devicetree.cb. BUG=268296760 BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Change-Id: I1c630e2efbdddd18a5423c79b73269e9b1be79c7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-18mb/google/geralt: Report SKU ID and panel ID for unprovisioned devicesYidi Lin
To make MIPI/eDP panel functional on unprovisioned devices, it requires passing SKU ID and panel ID info to the payload(depthcharge) to load the corresponded device tree for kernel. BUG=b:247415660 TEST=cbmem -1 |grep "SKU Code". Change-Id: Id2254729b7bd621d1e9bc520e8f40916d0f81030 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73076 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-17mb/google/skyrim/var/frostflow: Update Elan touchscreen power sequenceFrank Wu
Based on product spec v1.4, update T3 timing to 150 ms from 300 ms BRANCH=none BUG=b:269041202 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-02-17tree: Use __func__ instead of hard-coded namesElyes Haouas
Change-Id: I87e383ce2f28340dbc3c843dbf2ed0e47c00a723 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_AEI: ACPI Event Interrupts"Elyes Haouas
Change-Id: I58a4e4fbd1a43462147daa58a5fda767cfd59c06 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ADR: Address" commentElyes Haouas
Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17mb/google/dedede/var/dibbi: Update devicetree for enabling audioSam McNally
Enable HDA device and update jack codec HID from ALC5682I-VD to ALC5682I-VS. BUG=b:268309238 TEST=kernel detects audio DSP and rt5682s BRANCH=dedede Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-17mb/google/nissa/yaviks: Tuning eMMC DLL value for eMMC initialization errorchia-ling.hou
BUG=b:265611305 TEST=Reboot test 2500 times pass Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-02-16mb/google/brya: Add new baseboard hades with variants hadesEric Lai
Add a new baseboard for hades, an Intel RPL based reference design. Also, add variants for the reference boards hades. This commit is a stub which only adds the minimum code needed for a successful build. Need update gpio and memory DQ pins after final shchematic comes out. BUG=b:269371363 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-16mb/google/geralt: Pass XHCI_INIT_DONE to the payloadYidi Lin
BUG=b:269059211 BRANCH=none TEST=emerge-gralt coreboot Change-Id: Ia2ec6db332939f1ac629cda9a0784a12c92d91da Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73056 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-02-16mb/google/rex: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Mainboard variants to override the USB ports as per the target board design. TEST=Able to build and boot google/rex with all USB ports are working as expected. Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-16mb/google/brask/var/aurash: Initiate coreboot settingZoey Wu
Initial Aurash configuration base on moli design. 1. Set up gpio. 2. Add memory config. 3. There is no SD card setting on aurash, remove it from overridetree. 4. Follow moli psys schematic design. 5. Enable BT offload. BUG=b:269063331 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: Ia9088cc2937bab72c8c22af592392384a10616a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-02-15mb/google/brya/var/omnigul: Add memory parts supportJamie Chen
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) Samsung K3KL8L80CM-MGCT 2) Hynix H58G56BK7BX068 3) Micron MT62F1G32D2DS-026 WT:B 4) Micron MT62F512M32D2DR-031 WT:B 5) Hynix H58G56BK8BX068 BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com>
2023-02-15mb/google/brask/var/constitution: update gpio settingsMorris Hsu
Configure GPIOs according to schematics TEST=emerge-brask coreboot Change-Id: Ib27f1c334cad47b3be57f57b7cc8ca5530118328 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72945 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-15mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHzTarun Tuli
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements. For SCL, the t-high time is now over the min 600ns requirement for 400KHz operation (measure at over 700ns). Also, this change does not violate other parameters - rise time, setup time and hold time. BUG=b:264704732 TEST=Verified all timings meet spec now Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15mb/google/brya/acpi: Update checksum in NVPCF DSM subfunctionTarun Tuli
The NVPCF DSM subfunction specified a incorrect checksum. Update this function to the proper checksum of 0xaf. BUG=b:214581372 TEST=build Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15Revert "mb/google/brya/vell: Add PS1/PS2 cutoff point"Shon Wang
This reverts commit e30695dbe196ea42864ad03af799706eaae11f02. for meet thermal criteria, modify PS1/PS2 cutoff to default value BUG=b:229803757 BRANCH=brya TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72833 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-15mb/google/brya: Add Kconfig for TPM I2C busZoey Wu
Add TPM I2C for aurash to avoid TPM I2C fail. BUG=b:269050049 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: I1947d2e1189f46d8dab01837f75de7cb6e9e0579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14mb/google/skyrim: Create whiterun variantIsaac Lee
Create the whiterun variant of the skyrim reference board by copying the winterhold files to a new directory named for the variant. BUG=b:265955979 BRANCH=None TEST=emerge-skyrim coreboot and boot up on Whiterun Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7 Signed-off-by: Isaac Lee <isaaclee@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-14mb/google/skyrim: Add support for and select USE_SELECTIVE_GOP_INITMatt DeVillier
Add a FMAP region to support caching GOP-driver-modified VBIOS tables. Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP. Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP. BUG=b:255812886 TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS in CBFS, cached VBIOS data is used when not booting in recovery or developer modes. Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-14mb/google/hatch: drop include for puff baseboardMatt DeVillier
Commit 45b1da33c80a ("mb/google/hatch: split up hatch and puff baseboards") moved puff out from under hatch into its own mainboard dir, but this basebaord include was left behind. Delete it as it's not needed. TEST=build hatch variants Change-Id: I9045c52006fd232552541d68972d831c8b52da27 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14mb/google/rex: Set `SkipExtGfxScan` FSP-M UPDSubrata Banik
This patch overrides `SkipExtGfxScan` UPD as the Rex device is equipped with an on-board graphics device hence, skip scanning external GFX devices. BUG=b:228002764 TEST=Able to save ~1ms+ boot time on google/rex. FSP FPDT Data is showing the timestamp between those function calls. Without this patch: [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22 [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131 With this patch: `CheckOffboardPcieVga` is not getting called. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-13mb/google/skyrim/var/frostflow: Update Package Power ParametersJohn Su
Follow thermal table to modify setting. "stapm_time_constant_s" = "200" to "275" BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7fe05fe1c17258a3323b8d04302212e76a388797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-13mb/google/brya/var/lisbon: Update gpio tableRobert Chen
eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH. BUG=b:263548436 TEST=emerge-brask coreboot Change-Id: Iffbc9dc932325cdd2176b36795a2ff1b3690fbf8 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72941 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>