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2018-02-21mainboard/google/kahlee: Add tis_plat_irq_statusChris Ching
For variants that have a cr50 tpm, this enables faster polling when interacting with the tpm. BUG=b:72838769 BRANCH=none TEST=verified on grunt that irq is used and not timeouts for tpm Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20mb/google/poopy/variants/nami: Add Pmax settingGaggery Tsai
This patch adds the Pmax setting in device tree. The Pmax is from MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W. BUG=b:72138778 BRANCH=None TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage & ensure the Pmax value is passed to FSP-S. Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-20mb/google/kahlee/OemCustomize.c: Disable bank interleaveRichard Spiegel
AmdInitPost returns AGESA_WARNING. This is because AGESA by default enables bank interleaving, while the HW does not meet the requirements for it. Disable bank interleaving, thus clearing AGESA_WARNING. BUG=b:73118857 TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost() returned AGESA_SUCCESS". Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-17mb/google/fizz: Wait until display is readyDaisuke Nojiri
Fizz fails to show pictures on a type-c monitor because VBIOS runs before DisplayPort link is ready. With this patch, when firmware needs to display something, Fizz calls google_chromeec_wait_for_display to make sure display is ready. The penalty is up to 2 sec per boot in dev and rec boot. Normal boot won't affected unless there is EC update. BUG=b:72387533 BRANCH=none TEST=Verify screens are displayed on Fizz as follows: 1. Put DUT in normal mode 2. Flash EC image to trigger EC sync (critical update) 3. Trigger manual recovery (insert) 4. Hit ctrl+d to switch to dev mode (to-dev) 5. Confirm to reboot (dev warning) 6. Warm reboot (dev warning) 7. Cold reboot (dev warning) 8. Flash EC image to trigger EC sync (critical update) 9. Trigger manual recovery (insert) Change-Id: I90befe94f93e13904987acda50b2598d034b0031 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17soc/amd/stoneyridge: Normalize GPIO initJustin TerAvest
This makes the flow for GPIO initialization more closely follow that what is performed for other boards so that it's easier to read the flow (and stops relying on BS_WRITE_TABLES). BUG=b:72875858 TEST=Built and booted grunt, built gardenia. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23679 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-16mb/google/{soraka,poppy,nautilus}: Set psys_pmax to 45WNaresh G Solanki
Soraka, Poppy & Nautilus are designed to operate at max power of 45 Watt. Hence set psys_max to 45W. BUG=b:66066340 BRANCH=None TEST=Build and boot soraka. Change-Id: If6f624733830b462329b5f539c20e2aea664143e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/23757 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-02-16mb/google/zoombini/variants/meowth: enable FPMCU interruptVincent Palatin
Enable the micro-controller interrupt line as a real IRQ. BUG=b:71986991 BRANCH=none TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the number of interrupts incrementing and the MKBP event happening. Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-16google/gru: Fix GPIO_WP pull and polarity for ScarletJulius Werner
Turns out the write-protect GPIO polarity for Scarlet is different than for Kevin/Gru, and nobody ever told us. Also, it must not be configured with an internal pull-up or we'll not read the correct value. This patch fixes both issues. BRANCH=scarlet BUG=b:73356326 TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the right value in all cases. Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-15mb/google/poppy/variant/nautilus: Enable and configure DPTFSeunghwan Kim
This change enables DPTF and configures the policy. DPTF parameters were provided by internal power team. BUG=b:67877437 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23731 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-15mb/google/octopus: Add new boardHannah Williams
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp. TODO: Fix as per octopus schematic. Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23685 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14mb/*/spd: Use normal binary numbers (0b0010) instead of special format (2b0010)Jonathan Neuschäfer
This format (one hex digit, followed by 'b', followed by binary digits) is arguably useful, but also confusing. Use the more common format instead. Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-13mb/google/poppy: Fix the SPD for samsung_dimm_K4A8G165WBFurquan Shaikh
Original SPD provided by the vendor had bytes after 254 shifted by 16 bytes. This change fixes the SPD data based on the latest details received from the vendor. BUG=b:72749394 TEST=Verified that the device with this memory part boots to OS fine. Also, mosys is able to dump the right memory information. Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12mainboard/google/zoombini/variants/meowth: enable touchscreenNick Vaccaro
BUG=b:69011806, b:72179988 BRANCH=master TEST=Verify touchscreen on meowth works with this change. Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/23551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-02-12google/kahlee: Select HAVE_ACPI_RESUMEMarshall Dawson
TEST=Run powerd_dbus_suspend and resume with button press BUG=b:69614064 Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22732 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12google/snappy: enhance BigDaddy USB#2 2.0 strengthKevin Chiu
Fine tune 14" BigDaddy USB#2 2.0 strength: PERPORTPETXISET: 7 PERPORTTXISET: 1 IUSBTXEMPHASISEN: 3 PERPORTTXPEHALF: 0 this value could have USB#2 2.0 EA/function pass. BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23649 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11mb/google/fizz: Set SATA GPIOs in bootblockShelley Chen
Previously, we were seeing device boot into the recovery screen with error code 0x5a. This was root caused to the SATA GPIOs (specifically DEVSLP) not being initialized early enough, causing the SATA 1 link detection to time out and the device to reboot into recovery with 0x5a instead of booting into the OS as usual. BUG=b:69715162 BRANCH=None TEST=after flashing BIOS, set gbb flags to 0, then type reboot from the OS. Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mb/google/poppy/variants/nautilus: set oem_id, oem_table_id fields of ↵Naveen Manohar
acpi_header_t This change makes the Nautilus platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:68686020 TEST=Build, booted nautilus board. Verified kernel reads new strings. Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/23648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mainboard/google/meowth: Enable ECT againLijian Zhao
Previously ECT was disabled in commit 22401, on D0 stepping system and FSP version 7.x.20.52, disabling ECT will cause memory training failure and the system is stuck at post code 00D5h. BUG=b.72473063 TEST=Apply patch and build coreboot image, flash into meowth P0 system with D0 stepping silicon installed, system can pass memory training and boot up into OS. Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-10mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_tKaiyen Chang
This change makes Nami platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:70646770 TEST=Verify kernel reads new strings. Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23670 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10mb/google/grunt: Add ADAU7002 to devicetreeDaniel Kurtz
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S converter. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10mb/google/kahlee: Add grunt audio codecs to devicetreeDaniel Kurtz
Remove manually written asl entries for grunt's DA7219 and MAX98357A audio codecs, and replace them with equivalent devicetree entries. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-08mb/google/poppy/variants/nami: Revise AC/DC loadlinesGaggery Tsai
This patch revises AC/DC loadlines from VRTT reports. +----------------+-------+-------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------+-------+-------+-------+ | AcLoadline | 11 | 2.4 | 3.1 | 3.1 | | DcLoadline | 10 | 2.46 | 3.1 | 3.1 | +----------------+-------+-------+-------+-------+ BUG=b:72351128 b:72129954 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings are passed to FSP. Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07mb/google/fizz: Set Pmax to 120 for all SKUsShelley Chen
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4 (71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) + ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W. BUG=b:71594855 BRANCH=None TEST=Make sure correct pmax value is being passed into fsp Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23633 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-02-07google/kahlee/grunt: Fix 2 device specific variablesAkshu Agrawal
* micbias_lvl -> micbias-lvl * mic_amp_in_sel -> mic-amp-in-sel BUG=b:71875600 TEST=Checked in kernel the values are set Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/23603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07mb/google/poppy/variants/poppy: Enable EC_ENABLE_SECOND_BATTERY_DEVICENicolas Boichat
BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. Change-Id: I869bf08341b83f359066709e1e9c03af99482b2c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/23599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-07mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22Furquan Shaikh
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes). Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is removed from deep_sx_config as well. BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5. Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23594 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-06google/gru: Add another 512KB to the COREBOOT FMAP regionJulius Werner
With the new extra detachable UI elements, we're running out of space in Scarlet's RO CBFS. Thankfully, the GBB is still massively overdimensioned, so we can steal another half MB from there. This patch changes the FMAP for some boards that have already had production firmware releases. However, all the new changes are to the RO parts of the FMAP, so there shouldn't be a way this could cause a problem for updates. Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/google/kahlee: Fix grunt I2C rise/fall timesJustin TerAvest
I2C bus rise/fall times were measured as follows. Signals were generated with: - bus 0: manual i2c driver in depthcharge - bus 2,3: i2cdetect -r <bus_number> and then measured manually with an oscilloscope. BUG=b:72442912 Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/google/kahlee: Remove cmos.layoutRichard Spiegel
CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build kahlee. Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-06mb/google/eve: Enable HotPlug on PCIe root port for WiFiDuncan Laurie
Enable HotPlug for the PCIe root port that the WiFi device is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23512 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06google/kahlee: Initialize non-early i2c buses in mainboard_initDaniel Kurtz
Initialize non-early i2c buses in ramstage. BUG=b:69407112 TEST=Boot depthcharge w/ CLI enabled on grunt. devbeep => plays beep BRANCH=None Change-Id: I634a7a823cc393243841dbd55e52abe3f0e72c5a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/google/fizz: Determine PsysPl3 and Pl4 valuesShelley Chen
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid brownouts. According to Intel doc #560604, page 74, the max time window is 64ms (code=6) and the min duty cycle we can set is 4%. BUG=b:71594855 BRANCH=None TEST=Boot to OS and check MSRs using iotools for expected values Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06mb/google/nautilus: Work around the power issue of MIPI and USB camerasAndy Yeh
On EVT, the USB and MIPI cameras share the same power source. As a result, when the MIPI camera driver turns off the camera once probed, USB camera will be disconnected. To make USB camera work on EVT devices, we will need a hack in coreboot to leave the camera power always-on. BUG=b:72839352 TEST: Verified the MIPI and USB camera function on DUT board TODO: This power issue will be fixed on DVT build. Will revert this patch once confirmed power sources for MIPI and USB camera could be supplied individually. Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Reviewed-on: https://review.coreboot.org/23546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andy Yeh
2018-02-05mb/google/fizz: Get OEM ID and SKU ID from ECDaisuke Nojiri
This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails, it falls back to GPIO pins. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-05google/lars: Turn on keyboard backlight in romstageJenny TC
Cherry-pick from Chromium: a60ac10 [Lars: Turn on keyboard backlight in romstage] Use the keyboard backlight to provide indication that the system is booting. This is useful for determining that a system is in S0 and is running BIOS code. TEST=boot on Lars and see keyboard backlight come on early Original-Change-Id: I4fede6cff85f4487cedfbccf6cc24c6380d905e0 Original-Signed-off-by: Jenny TC <jenny.tc@intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I4b1fed10d9bd1ae1b265e848417836f816f252f3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Update GPIO mappingdavid
Combination of several commits from Chromium tree: 949037c [Lars: coreboot GPIO changes for EVT] c286789 [Lars: Set USB Type A current limit to 2A] 0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low] 4a0650d [Lili: Support touchscreen] Disable unused GPIOs based on schematic and adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK. Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A charging from the USB Type-A port. GPP_F_23 is set to NC currently and is floating, causing the on-board speaker to have no audio or the audio has noise; set to output/low. These commits bring lars' GPIO mapping in line with the Chromium tree. Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397 Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com> Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com> Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Update the MAINBOARD_FAMILY string in KconfigDuncan Laurie
Cherry-pick from Chromium: 99cd8f8 [lars: Update the MAINBOARD_FAMILY string in Kconfig] This string was left at the default for kunimitsu and should be updated to indicate the proper mainboard. Original-Change-Id: Icc0e162d57242e7b0610fb570ef1a8a45ee16e4f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4b70227c8cfdfe939e40ea6258d494337a2907b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Update SPD DataMatt DeVillier
Combination of several commits from Chromium tree: 3b875a2 [Lars: Update Memory ID for DVT board] b6d7c63 [Lili: Update Memory IDs] f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD] a6571bf [Lili: Update Memory IDs] 80e1841 [Lili: Update Memory IDs] 58d4487 [Lili: Fix memory string show error in spd data] These commits bring lars' SPD data in line with the Chromium tree. Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084 Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39 Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991 Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Add sdmode-delay property for max98357aMatt DeVillier
Adapted from Chromium commit: af3ec09 [Lars: Add sdmode-delay device property for maxim98357a] Add "sdmode-delay" as a device property for the maxim98357a codec. This speaker amp requires both SFRM & BCLK to active and stable before it is unmuted. If there is a BCLK and no SFRM, that results in a pop noise. Adding a configurable delay parameter for all Skylake platforms to allow sufficient time for the BCLK & SFRM on I2S to be stable before the amp unmutes itself to avoid a pop noise at the start of playback. Setting the delay to 5ms since the observed delay between SFRM and unmuting of the amp is around 2ms. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: update device properties for Nuvoton codecMatt DeVillier
Adapted from Chromium commit: 848ee3a [Lars: Add device properties for Nuvoton codec] Update sar-threshold, sar-compare-time, sar-sampling-time properties to match values in lars' Chromium branch. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Set new thermal parametersdavid
Cherry-pick from Chromium: 55c0eb3 [Lili: Set new thermal parameters] Set new parameters of DPTF for both Lars and Lili. The acoustic will have higher 1.6dB in transition mode, when using Lili fan table on Lars. Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Update DPTF settingdavid
Cherry-pick from Chromium: dff141b [Lars: Update DPTF setting] Original-Change-Id: I1f2686eced07c7fb1bde3c660df6d6efac607695 Original-Signed-off-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifd3e844688588b6d1c69459f75c0d7da93ba3688 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05mb/google/kahlee: Enable wlan card so it can be detectedMartin Roth
The wifi card was not being powered, and was being held in reset during PCI enumeration, so it was not being brought up. BUG=b:72738963 TEST=Verify wlan card shows up in lspci Change-Id: I5a1e83298af35aa80c67c75cd6ec0a2c3213891e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23552 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-02google/gru: Use newer version of Innolux P097PFG panel init codeLin Huang
There is a line artifact in the lower third of the display with the current initialization code. So update it with code provided by Innolux to fix this issue. BUG=b:69689064, b:72191820 TEST=boot on dru with an Innolux panel and artifact line disappear. Change-Id: I9679c4f7f706fd6cd2e1dba7ec79e772fe3f227a Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02mb/google/kahlee/mainboard.c: Create mainboard_pirq_dataRichard Spiegel
When booting kahlee, there's an error message: "Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist". This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data. BUG=b:70788755 TEST=Build and boot kahlee. Warning message must be gone. Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01mb/google/kahlee: always load and run display opromAaron Durbin
The kernel requires the display oprom is loaded *and* ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:72400950 Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23506 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31mb/google/kahlee: Add grunt cr50 supportJustin TerAvest
This commit adds an entry for H1/Cr50 into the devicetree for setting up ACPI entries for H1 communication. BUG=b:69250772 TEST=See probe messages in dmesg Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23514 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31mb/google/kahlee: Add grunt trackpad in devicetreeJustin TerAvest
This commit removes a manually written asl file in favor of configuring the trackpad through devicetree. BUG=b:72121803 TEST=cat /proc/interrupts with trackpad connected Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23508 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-31mb/google/poppy/variants/nautilus: Add gpio-keys ACPI node for PENHFurquan Shaikh
This change uses gpio_keys driver to add ACPI node for pen eject event. BUG=b:71329519 TEST=Verified using evtest that pen eject event results in events as expected. Change-Id: Ib293c2ca532c8ed9e2587143b1a69300cd9fa4e9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-30mainboard/google/zoombini/variant/meowth: enable FCAM_PWR_ENNick Vaccaro
Turn on power for front camera at startup in coreboot (needs to be set for factory scan). BUG=b:69011806 BRANCH=master TEST=none Change-Id: I2f31b19dfef5fe386b485dd675f0ff981288acf4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/23503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mainboard/google/zoombini/variant/meowth: fix SPD issuesNick Vaccaro
Fix incorrect settings in the Hynix 4GB and Samsung 2GB SPD files for meowth. BUG=b:69011806 BRANCH=none TEST=Confirm meowth with Hynix 16GB and meowth with Samsung 8GB solutions boot. Change-Id: Ia2ac564541b57647c3b605ce3389d74251490ca0 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23388 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30mainboard/google/zoombini/variants/meowth: enable I2C bus #2Nick Vaccaro
Enable I2C #2 for display backlight controller. BUG=b:69011806 BRANCH=none TEST=none Change-Id: I5440bd4265414c55458a73e293a9931145a158cc Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-30mainboard/google/zoombini/variants/meowth: Add rev 2 gpio changesNick Vaccaro
Change GPIO settings for meowth rev 2 boards. Changes include: - GPP_B7 set to no-connect - GPP_C1 set to no-connect - GPP_D8 set to no-connect - GPP_D9 (PP3300_WLAN_EN) set as output with initial value high - GPP_E9 (DCI_CLK) set to no-connect - GPP_E10 (DCI_DATA) set to no-connect BUG=b:72202352 BRANCH=none TEST=none Change-Id: I2e6d049faaa0a70b40ceb47aaf81a81d820dd4c1 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mainboard/google/zoombini/variants/meowth: Fix USB OC settingsNick Vaccaro
Set USB2 port 0 & 1 to use OC2 and OC3 respectively. Previous settings were causing false overcurrent conditions as OC0 and OC1 were used for other purposes. Remove initialization of unused usb3 ports, and configure the ports we use (usb3 ports 0 & 1) to use OC2 and OC3, respectively. BUG=b:72250084 BRANCH=none TEST=Verify meowth can recognize and boot off a kernel on USB drive. Change-Id: I528b67d80a1da84e5307facb40de545089979f57 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30mb/google/poppy/variants/soraka: Update _PSV for TCPUFurquan Shaikh
This change updates the passive setting for TCPU as per factory team recommendation. BUG=b:65467566 Change-Id: I081f63bdf811ff021c398f60efec9e6cccf462d5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23494 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30mb/google/poppy/variants/soraka: Enable mode-aware DPTFFurquan Shaikh
This change selects EC tablet event and provides trip point temperatures for tablet and non-tablet mode so that DPTF can be supported depending upon device mode. BUG=b:65467566 TEST=Verified by changing modes that the trip point temperatures are updated in the OS (/sys/devices/virtual/thermal/thermal_zone{2,3,4,5}). Change-Id: I071868982fa87821550b870a6d8050cf2a030b49 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23463 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30chromeec: Decouple EC tablet event and TBMC deviceFurquan Shaikh
This change decouples EC tablet event and TBMC device by guarding TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It allows mainboards to use tablet events without having to define a TBMC device. BUG=b:72554519 Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30mb/google/kahlee: correct comments in baseboard gpio.cAaron Durbin
The gpios for 147 and 148 are connected to PCH_I2C_HUB_SCL and PCH_I2C_H1_TPM_SDA, respectively. Fix the comment. BUG=b:64140392 Change-Id: Ibebf6ce7d9fb26276b12b9c9844c260413f0337e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30mb/google/kahlee: mark h1 bus as early init for gruntAaron Durbin
Since the h1 i2c bus is required for verstage mark the bus as needing to be initialized early. That way, the bus is initialized in bootblock prior to verstage. BUG=b:70232394,b:69250772 Change-Id: Ice8525e08ccb438bc468d4c8bd311f72eddc7eb6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-29google/scarlet: Add initialization sequence for Innolux P097PFG panelLin Huang
Innolux didn't deliver a working init sequence yet for devices without OTP programming. The sequence in this change has been derived from a register dump of a mostly working panel with OTP. It is not meant to be final, but to make devices with unprogrammed OTP work, while Innolux is figuring out a proper sequence. There is a known issue with an artifact line in the lower third of the display. Change-Id: I7096506208e4cb29c5f31a7ac502231a6c23ac92 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-29rockchip/rk3399: Support LONG_WRITE type in MIPI DSILin Huang
Some panels need to transfer initial code, and some of them will be over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi dsi transfer function to support it. Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-29google/fizz: Adjust PL2 and PsysPl2 values for power lossShelley Chen
Set PsysPl2 values to 90% of max adapter power for all types of adapters (typeC and barrel jack) to account for a 10% power loss from the adapter to the soc. BUG=b:71594855 BRANCH=None TEST=reboot device and make sure Pl2 and PsysPl2 MSRs are properly set with iotools rdmsr command on both U42 and U22 skus with both typeC and barrel jack power adapters. Change-Id: I8425c6d4d669449eccb9324ff58ff6d1662c5c43 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-29mb/google/kahlee: Fix I2C bus 1 timing for GruntJustin TerAvest
I measured the rise and fall times for I2C bus 1 from userspace manually, using "i2cdetect 1" called from userspace and an oscilloscope. This commit fixes the values there to reflect reality. BUG=b:72442912,b:70232394 Change-Id: I4f593cb2674006060cad9a77753c23f7d9828c9b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23459 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-26mb/google/poppy/variants/soraka: Configure unused pins as NCFurquan Shaikh
This change configures unused pins as not connected. Change-Id: I6779d9fba73da8fb2faa08ad5d2236b813105720 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-26mb/google/poppy/variants/nautilus: Update camera power enable GPIOsFurquan Shaikh
This change updates the camera power enable GPIOs as per the latest schematics. With this update, since one of the enable GPIOs is using a UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that FSP-S does not re-configure the UART0 GPIOs. BUG=b:68964831 Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26mainboard/google/zoombini/variant/meowth: add PCH_WP_ODNick Vaccaro
Configure GPP_H12 as an input for PCH_WP_OD. BUG=b:72202352 BRANCH=none TEST=none Change-Id: Ie5b60644a24d745add4d0d38c1421974b8a0017b Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Add Grunt touchscreen supportJustin TerAvest
This commit adds support for an Elan touchscreen device connected over I2C via devicetree. BUG=b:72121803 TEST=Confirm the device is probed for. Change-Id: Ia9e427dbeab9088f77e3cd751b561f7b9a8cb400 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25mb/google/kahlee: Add Grunt devicetree i2c bus cfgJustin TerAvest
I2C bus configuration is generally set up in devicetree.cb. This change establishes listings for the buses so that they can be used (though followup changes should update the buses to have correct timings). BUG=b:72121803 Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Select DRIVERS_I2C_GENERICJustin TerAvest
This is required to add support for I2C devices on Kahlee to ACPI tables via devicetree.cb. Without this, operations are not emitted for I2C devices and the proper ACPI table entries are not generated. BUG=b:72121803 Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25mb/google/kahlee: Correct grunt HWID in GBBJustin TerAvest
Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296 comes from the lower four numbers from running: $ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST')) BUG=b:72436450 Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25mb/google/poppy/variants/nami: Disable SATAKane Chen
This change disables SATA controller in order to make SATA IP enter low power status. BUG=b:72332817 TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status and verify SATA IP enters low power state Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23354 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25mainboard/google/zoombini: add ACPI entry for cr50Caveh Jalali
This adds coreboot device tree entries on zoombini & meowth for the cr50. Also, fixes the GPIO pin IRQ settings to be falling edge. This is based on what we do for fizz. BUG=b:71722449 TEST=booted to linux on meowth: tpm_version command now sees the cr50. localhost ~ # tpm_version TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 localhost ~ # uname -a Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux localhost ~ # and we see interrupts when talking to the cr50: localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru pts 84: 4687 IO-APIC 84-edge cr50_spi TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 84: 4799 IO-APIC 84-edge cr50_spi localhost ~ # Change-Id: I9d503334502503ef49515e4a8736d967bc454a98 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-25mb/google/poppy/variants/nami: Enable elan touchpad wakeup system from S3/S0ixVan Chen
BUG=b:71839089 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. powerd_dbus_suspend 3. touch touchpad to wakeup system 4. localhost ~ # cat /var/log/eventlog.txt | 2018-01-21 17:01:59 | S0ix Enter | 2018-01-21 17:02:04 | S0ix Exit | 2018-01-21 17:02:04 | Wake Source | GPIO | 80 Change-Id: Ie550cfa3f7b5fd105f89c16076d428743392d0e4 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23363 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-24mb/google/fizz: Add AC/DC loadline settingsGaggery Tsai
This patch adds AC and DC loadline settings since vr_config_enable is set. Without correct AD/DC loadline settings, VRs reported incorrect VID values which caused CPU freqency clipping. The clipping reason could be retrieved from MSR 0x64F. From VRTT report, the AC/DC loadline resistances are within spec, we can use default value defined in Table 6-1, doc #543977. BUG=b:70646304 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline settings from DCI to ensure the values were programmed correctly. Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23349 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23mainboard/google/fizz: Tune audio i2c parametersShelley Chen
Tune I2C params for I2C bus 5 to ensure that the frequency does not exceed 400KHz. BUG=b:65058277 BRANCH=None TEST=Measured bus frequency for audio <= 400MHz Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23grunt: Enable TPMChris Ching
Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create the appropriate selection based on selected board, and if grunt then define the I2C address. BUG=b:69416132 BRANCH=none TEST=make all Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22960 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mb/google/reef,sand: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-23google/kahlee/BiosCallOuts.c: Remove platform_FchParams_resetRichard Spiegel
Function platform_FchParams_reset() is now an empty function, remove it, its header declaration and its use. BUG=b:64140392 TEST=Build kahlee. Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO tableRichard Spiegel
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data from agesa_board_gpios[], wrap format and delete agesa_board_gpios[] and get_gpio_table(). Then remove the get_gpio_table() call from BiosCallOuts.c. Finally, remove get_gpio_table() from google/kahlee/variants/baseboard/include/baseboard/variants.h. BUG=b:64140392 TEST=Build grunt. Build and boot kahlee, recording serial output. Search for "stage bootblock" and "stage ramstage", indicating GPIO being programmed. Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23soc/amd/stoneyridge/southbridge.c: Create a GPIO programming functionRichard Spiegel
Create a GPIO programming function that can be called from multiple stages (bootblock, romstage and ramstage) that will program only the GPIO specific to the particular stage. Add dummy table to kahlee, grunt and gardenia to be able to test a build. BUG=b:64140392 TEST=Build kahlee, grunt and gardenia with GPIO programming call at bootblock. This call is removed before commit, so bootblock.c is not committed. Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23mb/google/poppy/variants/nami: Remove iccmax setting from devicetreeFurquan Shaikh
Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings) provides correct iccmax settings for kbl-u based on the SKU. Thus, there is no need to override these values in devicetree. This change gets rid of iccmax settings in the nami devicetree. Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-22mainboard/google/zoombini: mrc cacheCaveh Jalali
this enables the MRC recovery cache for zoombini & variants. the Kconfig options are: HAS_RECOVERY_MRC_CACHE MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN one note of caution: early board builds will likely fail to boot with: tlcl_extend: response is 0 tlcl_extend: response is 0 tlcl_lock_nv_write: response is 0 tlcl_lock_nv_write: response is 28b Failed to lock rec hash space(1f) Saving nvdata hard_reset() called! the fix is to boot into recovery once, then it's business as usual. using servo, this can be done with: dut-control power_state:rec BUG=b:71785303 BRANCH=chromeos-2016.05 TEST=boots on meowth... Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23298 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22mainboard/google/zoombini: add EC to ACPI tablesCaveh Jalali
this adds missing ACPI entries for the EC, CPU, and power button. also, the EC to AP wakeup pin assignment is fixed. BUG=b:71819257 BRANCH=chromeos-2016.05 TEST=booted on meowth. /sys/class/power_supply now gets populated. Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/23237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-01-22mb/google/fizz: Remove IccMax settings from DTGaggery Tsai
This patch removes IccMax settings from device tree since they are handled in SoC code from patch e1a75d. BUG=b:71369428 BRANCH=None TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure the IccMax settings passed to FSP are from SoC code. Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: enable PCH_FP_PWR_ENVincent Palatin
Turn on the load switch to the FP MCU at startup, so the kernel can detect it and use it. The load switch enable pin is connected to the GPP_A11 PCH pin (aka PCH_FP_PWR_EN). BRANCH=none BUG=b:71986991 TEST=on Meowth, see the kernel detecting a cros_fp device at startup: [ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected. [ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: configure FP MCU SPI deviceVincent Palatin
Configure the FP MCU interface on GSPI1. BRANCH=none BUG=b:71986991 TEST=boot on reworked Meowth with a ZerbleBarn board attached to GSPI1 and see the cros_ec kernel driver detecting it. Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-18mainboard/google/zoombini/variant/meowth: add memory optionsNick Vaccaro
Add support for new memory stuffing options that will appear on the P1 meowth boards. new strap setting - associated SPD file ---------------------------------------- 0b001 - Hynix_H9HCNNN8KUMLHR_1GB.spd.hex 0b010 - Samsung_K4F6E3S4HM_2GB.spd.hex 0b011 - Hynix_H9HCNNNCPUMLHR_4GB.spd.hex BUG=b:69011806 BRANCH=none TEST=none Change-Id: Ief07f3de351d01cbc195b785c36e96de0cbf7ddb Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17google/fizz: Fix barrel jack values for U42 and U22Shelley Chen
Our current U22 skus (celeron and i3) actually don't support PL2, but making sure that if we do decide in the future to use it to make sure PL2 and PsysPl2 values are set appropriately. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42 and 65W with barrel jack for U22. Change-Id: I084d0320128a6e05948023520a30c497c41be23b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17mb/google/poppy: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17mb/google/nautilus: Add MIPI camera asl files for IMX258 and DW9807Andy Yeh
* Add IMX258 sensor entity * Add DW9807 VCM control entity * Enable CIO2 and IMGu in devicetree.cb TEST: Verified the MIPI camera function on DUT board Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Move PMIC specific objects to appropriate scopeRizwan Qureshi
Right now the poppy baseboard camera topology allows to add maximum of 2 sensors. The sensors can be of different vendors. The current ASL code structure doesn't allow sensor customization. Moving PMIC specific objects from sensor objects to PMIC scope and having separate sensor ASL files will help in unbinding the PMIC and sensor objects and allow some customizations. BUG=None BRANCH=None TEST=Build and boot soraka, make sure both camera's are working fine and also verify that the generated DSDT looks fine. Change-Id: I63ae1a685b78bda212c5c48a4c2dc744164a3cb5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Split ports and endpoints config for CIO2Rizwan Qureshi
The variant boards can have a custom endpoints, splitting the ASL code aids customizing the endpoints as per the variant board setup. BUG=None BRANCH=None TEST=build boot soraka, verify that the cameras are working fine and generated DSDT tables are same as before. Change-Id: I5f1cded25bfb6a7baf18b211f9773dfecdc2f264 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-15mb/google/poppy/variants/nami: Enable elan touchpadvan_chen
BUG=b:71838954 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: Elan Touchpad Change-Id: I14471d1473a3b3ecf15aaf362b47874704cd3bf0 Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-13mainboard/google/kahlee: Finish GPIO90 setup for GruntMartin Roth
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly, but these additional registers need to be set to use it as a GPIO. - Split structures into variant specific versions. These will be moved into the variant tree in a follow-on patch - Set GENINT_DISABLE bit - Disable interrupts for this GPIO. BUG=b:71867096 TEST=Build and boot grunt. Verify registers are set correctly. Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23228 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13mainboard/google/kahlee: Fix GPIO tableMartin Roth
The GPIOs that are being set low had the wrong value getting set. FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE. BUG=b:70234300 TEST=Build and boot Grunt Change-Id: I16792b76252506a43aac92738b04096ae3fde01c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-13google/kahlee/grunt: Add grunt touchpad ASLDaniel Kurtz
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD, respectively. Since grunt is the 'baseboard', put its configuration under baseboard, and include it from the grunt variant. BUG=b:71820409 TEST=Boot grunt to kernel, use evtest to test trackpad. TEST=Boot kahlee to kernel, use evtest to test trackpad. Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23232 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 21:34:03 +0000