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2021-04-19Revert "mb/google/guybrush: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Change-Id: I921dc5c814e5187dce283eeff43075b59885723a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/hatch: Guard ChromeOS fmd selection on CHROMEOSMatt DeVillier
Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS is selected, so non-ChromeOS targets use the default x86 FMAP. Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18mb/google/mancomb: Remove PS/2 mouse configEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add GPIO override tableKarthikeyan Ramasubramanian
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has a voltage rating of 3.3 V. The schematics has been updated to bridge the gap. So enable the speaker amplifier by default and add a gpio override table to disable the speakers before board version 2. Also update the codec ACPI HID name for the kernel machine driver to probe the codec successfully. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state is high. Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush: Enable AMD I2S Machine DriverKarthikeyan Ramasubramanian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for machine driver is populated. Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add FPMCU configrationIvy Jian
Enable CRFP in devicetree and configure GPIOs. BUG=b:182201937 BRANCH=None TEST=Boot into OS and confirm FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-16mb/google/guybrush: Enable backlight in the OSMartin Roth
Add ACPI code to enable the backlight when we enter the OS. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure HID over I2C related GPIO as level-triggeredVictor Ding
Both touchpads supported by zork use level-triggered wakeup signal. BRANCH=zork BUG=b:172846122,b:182911201 TEST=1. cros build-ap -b zork 2. both Synaptics and ELAN touchpads work fine on Vilboz 3. Wakeup source is correctly reported on Vilboz Signed-off-by: Victor Ding <victording@google.com> Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure IRQs as level triggered for ELAN touchpadVictor Ding
Based on the datasheet provided by ELAN, the /INT pin is "low active" and "indicates touchpad likes to send data to system(host) when low". The signal is level-triggered. BRANCH=zork BUG=b:172846122 TEST=cros build-ap -b zork Signed-off-by: Victor Ding <victording@google.com> Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/dedede/var/galith: support Audio AMP I2C/Auto modeFrankChu
support audio AMP selection with fw_config. BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ieb169c69a6716082dd218d05479bca46bbc09a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-16mb/google/dedede: Add AUDIO_AMP FW_CONFIG in devicetreeFrankChu
Add AUDIO_AMP ports bit field in devicetree. UNPROVISIONED 0 MAX98360 1 RT1015_I2C 2 RT1015P_AUTO 3 BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I54f1e44036857dc00df074c38fde0fa82e589320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/dedede/var/storo:Add P-sensor for storoZanxi Chen
Modify GPIO_D22/D23/E11 configuration for P-sensor BUG=b:185214363 BRANCH=dedede TEST=built storo firmware and verified P-sensor function Change-Id: Ia2df1a227b04688a6b98384cd3a4e63023c0c1d9 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16mb/google/brya: Configure TCSS OC pins for bryaMaulik V Vaghela
TCSS OC pins has not been correctly configured for brya. This patch fills the value from devicetree to correct the OC pins mapping BUG=b:184653645 BRANCH=None TEST=check if UPD value has been reflected correctly Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16mb/google/octopus: Add log for ssfc update codecEric Lai
Add log to show the codec has been disabled. BUG=b:185193926 TEST=cbmem -c | grep disabled, can find the codec name Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ce7e435ce73beb2a5cbf5883905554227b1989b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-04-16mb/google/guybrush: Implement tis_plat_irq_statusRaul E Rangel
BUG=b:185397933 TEST=boot guybrush and no longer see tis_plat_irq_status warnings Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9b67cb59221d4e355df8e8a2205e03ead7dba51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/{guybrush,mancomb}: Add VBOOT_VBNV_OFFSETRaul E Rangel
This is the same as zork. BUG=b:184126844 TEST=Boot guybrush in developer mode and switch to normal mode. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/guybrush: Sort VBOOT_EARLY_EC_SYNCRaul E Rangel
BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I658372d082a8276f15c7165fe4104de4613fe7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15mb/google/guybrush,mancomb: include soc/gpio.h in baseboard/gpio.hFelix Held
This include provides the GPIO_x definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12a0d95f79658f3852132876e92c389b715f3001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52358 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: move include to the files where it's usedFelix Held
platform_descriptors.h is unrelated to the contents of baseboard/gpio.h where it was included, so move the includes to the files where it is actually needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: include amdblocks/gpio_defs.h in baseboard/gpio.hFelix Held
amdblocks/gpio_defs.h provides the definitions of GEVENT_x. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/kahlee: use defines for GEVENT numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I353f0d241391dd1122c85866a74984b95ed54770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52305 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15herobrine: sc7280: Provide initial mainboard supportT Michael Turney
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15mb/google/guybrush,mancomb: use EC_SCI_GPI in espi_sci_sources structFelix Held
The board's ec.h file defined EC_SCI_GPI as GEVENT_24, so use that definition in all places in the mainboard code instead of a mix of the board specific define and the SoC's GEVENT number define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46525ed24e9993acd3d850959dd63761a690d5df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15mb/google/brya: Add FPMCU power controlEric Lai
Enable CRFP power control in gpio table. RST needs to drive low before PWR enable. Since reset signal is asserted in bootblock, it results in FPMCU not working after a S3 resume. This is a known issue. BUG=b:181377402 BRANCH=None Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52185 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/dedede/var/kracko: Add LTE modem supportTony Huang
Add LTE modem to devicetree Configure GPIO control for LTE modem BUG=b:178092096 TEST=Built image and verified with command modem status Change-Id: Id8f483e1132a08500fbe950711cc84197ce40b12 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-15mb/google/dedede/var/sasukette: Enable Wifi SAR for sasuketteTao Xia
BUG=b:185084331 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ie982741cb7b328623cf27f41c31f819e8cdb7bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-15mb/google/zork: fine tune stamp_boost parameter for dirinbozKevin Chiu
The new discovery from Google & AMD, the value currently used STAPM Time Constant of 1640 is reducing real PPT TSP from the target 4.8W to 4.68W. Furthermore, when using the "default" STAPM Time Constant of 1400, the actual real PPT TSP becomes 4.89W. Operating at this default settings therefore uses a higher real PPT TSP, which results in a significant performance improvement. BUG=b:175364713,b:184902568 BRANCH=zork TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: fine tune stamp_boost parameter for gumbozKevin Chiu
The new discovery from Google & AMD, the value currently used STAPM Time Constant of 1640 is reducing real PPT TSP from the target 4.8W to 4.68W. Furthermore, when using the "default" STAPM Time Constant of 1400, the actual real PPT TSP becomes 4.89W. Operating at this default settings therefore uses a higher real PPT TSP, which results in a significant performance improvement. BUG=b:184902568 BRANCH=zork TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I102c1c5f8215a6c5f7a4451f5731167c32e27c90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52313 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14mb/google/dedede/var/boten: Add custom Wifi SAR for botenflexStanley Wu
Add wifi sar for botenflex. Due to fw-config cannot distinguish between boten and botenflex. Using sku_id to decide to load botenflex custom wifi sar. Detail reason for using sku_id in b:182433707. BUG=b:182433707 TEST=build and test on boten/botenflex Cq-Depend: chrome-internal:3686313 Change-Id: Id3f2529a7ad56ff306df98f77cda556656da52a5 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-14mb/google/volteer: Update collis device treeFrankChu
Update device tree override to match schematics. BUG=b:182227204 TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ib1698504cc0b377659fa60b4fae25227b5823753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-14mb/google/volteer: Add GPIO to collis supportFrankChu
Add support for gpio driver for collis BUG=b:182227204 TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ief225093bf93137384b64327a1c66576c9a5193a Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-14mb/google/brya: Enable CSE Lite SKUTim Wawrzynczak
The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:183826781 TEST=50 cold reboot cycles Cq-Depend: chrome-internal:3758108 Change-Id: Ib3a1a9f8ac51bdab8858b2764d5bc0f6f07987cc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-14lillipup: provide additional VBT for lillipup OLED skuKevin Chang
Lillipup add two sku for OLED panel. Additional VBT is necessary to modify PWM source from VESA eDP AUX interface BUG=b:183630802 TEST=emerge-volteer coreboot-private-files-baseboard-volteer check vbt_oled.bin is under build folder and check in CPU log. Cq-Depend: chrome-internal:3744227 Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52150 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14mb/google/cherry: Add MediaTek MT8195 reference boardYidi Lin
TEST=boot from SPI-NOR and UART works fine. Change-Id: I279b3d2da8a30b38686005212f6c019a9a646874 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-13dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak
DPTF HIDs are different per-platform going forward, so refactor these into SoC-specific structures which the DPTF driver can query at runtime for platform-specific information. Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-12mb/google/mancomb: Temporary fix to set eSPI muxEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-12mb/google/mancomb: add DXIO and DDI descriptorsEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-11mb/google/dedede: Enable HECIAseda Aboagye
This commit enables HECI such that interface can be used from userspace on the dedede mainboards. BUG=b:184219504 TEST=Build and flash drawcia, verify that Intel Flash Programming Tool can communicate with the Converged Security Engine. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I5b28c471d6554a5e14538073d48ef47da05936fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-11mb/google/zork/vilboz: Update register parameters for sx9324 tuningFrank Wu
To update the sx9324 registers after RF team fine-tuned the parameters. BUG=b:172397658 BRANCH=firmware-zork-13434.B TEST=build coreboot and verify the sx9324 function Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ief85bc61952144a1d7a151100d89938517078ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51936 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10mb/google/brya: Change GPP_E16 default to highAlex Levin
To enable WWAN we want to release it from reset start. BUG=b:180166408 TEST=WWAN enumerates on brya Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52199 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/google/mancomb: Add Codec configrationEric Lai
Enable I2C2 in devicetree and fill ACPI information for Codec. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add Bluetooth configurationEric Lai
Configure the BT disable GPIO to logic low in order to enable Bluetooth. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Update GPIO configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Enable AP <-> H1 communicationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add initial I2C configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDsStanley Wu
Enable Acoustic noise mitigation for boten and set slew rate to 1/8 which is calibrated value for the board. BUG=b:180668001 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I75851bd7c279feeab4ab94f4c82d55bf0e5ce316 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-09mb/{google/jecht,intel/wtm2}: Remove NOOP APM finalize callArthur Heymans
The intel/soc/broadwell smihandler has no handler for this APM call. Change-Id: I2bcec7cce00d433a197a9e2fb01434a2998e1452 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52167 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/google/volteer/var/lindar: Configure unused GPIOs as NCKevin Chang
Configure unused GPIOs as NC BUG=b:180830117 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I0ba51dc262ccbf22b45d3be4b65e006f92587fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-09mb/google/asurada: early-init eMMCWenbin Mei
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, Depthcharge needs it 20ms after started) so we have to start initialization in coreboot. On Hayato Chromebook this can save ~100ms in total. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51973 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/google/asurada: select mmc storage configWenbin Mei
Select mmc storage config for asurada. Build MTK host mmc driver. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-08mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boardsFelix Held
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMPFrank Wu
Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180. AMDI1015 -> AMD platform with RT1015 10021015 -> AMD platform with RT1015p Reference: https://www.spinics.net/lists/alsa-devel/msg124694.html BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52127 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Unmask eSPI keyboard IRQRaul E Rangel
PS/2 keyboard used IRQ 1. BUG=none TEST=Boot guybrush and see internal keyboard working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52143 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Remove PS/2 mouse configRaul E Rangel
Guybrush doesn't have a PS/2 mouse. BUG=none TEST=boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: PCIe GPIOs - enable enables, disable resetsMartin Roth
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WWAN & WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/brya: Change GPP_D15/D16 default to lowEric Lai
WFC Camera driver will control the power sequence. Therefore, set default to low. BUG=b:184024459 TEST=abuilds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-08mb/google/dedede/var/metaknight: Add support to handle pen detectionDavid Wu
Update devicetree and gpio setting of metaknight to handle pen detection. BUG=b:180426949 TEST=Build and check behavior is expected. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ieeca20eff57b16217a13d996dca3f662911f3e5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-07mb/google/guybrush/port_descriptors: add dummy descriptorsFelix Held
This is a temporary workaround for a bug that breaks graphics due to some power management issue. Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptorsMartin Roth
pcie_rst isn't working correctly, so use the AUX resets to reset the PCIe devices before training. BUG=b:182202136 TEST=See PCIe devices train & enumerate Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/google/guybrush: add DXIO and DDI descriptorsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/google/mancomb: Enable USB ports in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-07mb/google/mancomb: Enable PCIe devices in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add initial fch irq routingEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/52117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add eSPI GPIO back to init tableEric Lai
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Configure UART0 gpio in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARINGEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable early EC Software SyncEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-06intel/tigerlake: Add Acoustic featuresShaunak Saha
On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06Revert "mb/google/guybrush: Disable GFX"Raul Rangel
This reverts commit 52e61945588bc327844acc4658426861d63ad189. Reason for revert: Graphics actually works now. I should have abandoned this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I83aac3a2c616bb434706f23e36549760bc764080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-06mb/google/volteer/var/lindar: Increase Goodix touchscreen reset delay to 180 msKevin Chang
1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. BUG=b:181711141 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I82222ca094eead7e9e691857e128243cfe7c310e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-06Lindar/Lillipup: Enable Bayhub SD card reader power-saving modeKevin Chang
Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup. BUG=b:173676531 TEST=Boot to OS and test with SD card function. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-06mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625Jitao Shi
Config ANX7625 line data end same time on all line. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-06mb/google/guybrush: Disable GFXRaul E Rangel
This is locking up the OS. For now this will unblock booting. BUG=b:183971103 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-06mb/google/dedede/var/cret: Support LTE moduleDtrain Hsu
Add LTE module support into devicetree and associated GPIO configuration. BUG=b:183774169 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I14684bb30e46bf845a401649f56b16b60db379e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-06mb/google/dedede/var/cret: Add audio supportDtrain Hsu
Select the drivers for DA7219 codec and MAX98360A spk amp BUG=b:183771323 BRANCH=dedede TEST=emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I3fd7c374fc8214e25a28fb9ba62a9c8473d3f755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51841 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/kukui: fix the issue of getting error panel_idxuxinxiong
Current get panel_id is over sku_id() >> 4, but sku_id is combined with wfc_id/lcm_id/sku_id, so the panel_id value is wfc_id << 4 | lcm_id() in fact. When wfc_id is not 0, the panel_id will be wrong. So only get the low 4 bits for the panel_id. BUG=b:183779755 BRANCH=kukui TEST=emerge-kukui Change-Id: I63e0c8a2719462a9b979afe52a27c78b9fc804e8 Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-06mb/google/kukui: katsu: update the EDID and initial codeSunway
The EDID and initial code are provided by STA (the vendor). BUG=b:183969078 TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/brya: Move early GPIO config earlierTim Wawrzynczak
The recent refactor of console UART GPIOs to mainboard's bootblock caused brya boards to lose the first ~5 lines of the logs from bootblock. Rename bootblock_mainboard_init to bootblock_mainboard_early_init so that the UART pads will be ready by the time the console is initialized. BUG=b:184319828 TEST=First lines from report_platform.c are now seen in UART output Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-06mb/google/zork: update DRAM table for morphiusKevin Chiu
Add Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb index was generated by gen_part_id BUG=b:184024142 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz/Vilboz360 LTEFrank Wu
Loading wifi_sar-vilboz-2.hex for vilboz LTE sku. Loading wifi_sar-vilboz-3.hex for vilboz360 LTE sku. BUG=b:183902165, b:176211194, b:183913210 BRANCH=firmware-zork-13434.B TEST=Build coreboot and load the wifi sar table by fw_config Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-05mb/google/guybrush/var/guybrush: Add Codec and Speaker configrationKarthikeyan Ramasubramanian
Enable I2C2 in devicetree and fill ACPI information for Codec and Speaker amplifiers. Pass correct IRQ GPIO for headset jack. BUG=None BRANCH=None TEST=Ensure that the Codec and Speaker Amplifiers are detected in i2cdetect. Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05mb/google/guybrush: Add Bluetooth configurationKarthikeyan Ramasubramanian
Configure the BT disable GPIO to logic low in order to enable Bluetooth. Add USB ACPI configuration for BT device. BUG=b:182201890 TEST=Build and boot to OS. Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05mb/google/guybrush: Enable camera power GPIOIvy Jian
Configure camera power GPIO to high BUG=b:182207799 TEST=Build and boot to OS then checked camera device existence with lsusb Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-05mb/google/guybrush: Update GPIO configurationMartin Roth
Initialize all eSPI signals including PCIE_RST0_L early for EC communication. - Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is a temporary workaround until PCIE_RST_L comes up on its own. - Make sure all GPIO muxes initialized early are re-initialized. BUG=b:183340503 TEST=Boot Guybrush Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05mb/google/mancomb: Add ACPI support for Chrome ECEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable eSPI VW SCI eventsEric Lai
Mancomb does not have a dedicated SCI pin so it uses VW. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable Chrome EC SKUID and BOARDIDEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I70283c8d93b5cbabdaf5a8ab947d5f8444940dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/51626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Add smihandlerEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/51625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable Chrome ECEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/dedede/var/sasuke: Update DPTF parametersSeunghwan Kim
Remove TSR2, use DPTF parameters from internal thermal team. BUG=b:183749595 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I3182b96bf36c8d07299fe435a29e6b8c0b8a6927 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-05mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audioSeunghwan Kim
Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (< 400 kHz). Measured I2C frequency just as below after tuning: I2C0(touchpad): 385 kHz I2C4(audio): 380 kHz BUG=b:180335053 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-05mb/google/dedede: add lalala variantAaron Durbin
The Lalala variant is a design that differs only in replacing Cr50 with a discrete TPM part. BUG=b:184151664 Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2021-04-05mb/google/dedede: add discrete TPM 2.0 configurationAaron Durbin
There are forthcoming designs that will be utilizing a discrete TPM 2.0 solution. Split the existing dedede configuration options so future mainboard variants can easily select the appropriate Kconfig option using the newly introduced options: - BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 - BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 The existing variants all select the former option, BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those designs currently utilize Cr50. BUG=b:184151664 Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05mb/google/brya: Enable south XHCI ports 1 and 2Furquan Shaikh
FSP v2081 has a bug where it uses the information about south XHCI ports to enable TCSS XHCI ports. This change works around this bug by enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0 already enables south XHCI port 1 in overridetree.cb, however, it is still enabled in baseboard/devicetree in case more variants are added to brya before FSP is fixed. BUG=b:184324979 TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled. Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-05nb/intel/sandybridge: Drop `pci_mmio_size`Angel Pons
There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02mb/google/zork/vilboz: Fix audio test failure on LTE SKUJohn Su
Use board id to switch acp_i2s_use_external_48mhz_osc enable. BUG=b:181720406 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I085c39accd82bf72e4ebbc0394382ed4a7d4e901 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-04-02mb/google/guybrush: Enable early EC Software SyncKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync is complete. Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>