diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-03-18 16:39:49 +0800 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-04-05 16:41:14 +0000 |
| commit | 7bbcdc2f207aa2ed42f713aa455ff698f958ab24 (patch) | |
| tree | 01893ffbe8f0d145a6e13a451513bbb635b651a3 /src/mainboard/google | |
| parent | e93e693173ca486d6b4674f731f6c9bbeab6bf81 (diff) | |
mb/google/mancomb: Add ACPI support for Chrome EC
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/mancomb/dsdt.asl | 11 | ||||
| -rw-r--r-- | src/mainboard/google/mancomb/variants/baseboard/devicetree.cb | 5 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/mancomb/dsdt.asl b/src/mainboard/google/mancomb/dsdt.asl index 7b8982a645..73a2ea5da1 100644 --- a/src/mainboard/google/mancomb/dsdt.asl +++ b/src/mainboard/google/mancomb/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <variant/ec.h> + DefinitionBlock ( "dsdt.aml", "DSDT", @@ -13,4 +15,13 @@ DefinitionBlock ( #include <acpi/dsdt_top.asl> #include <soc.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } } diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index db21dd4e26..c4ef3f546b 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -42,5 +42,10 @@ chip soc/amd/cezanne device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end end # domain end # chip soc/amd/cezanne |