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2022-04-29mb/google/brya/var/agah: Change Aux settings to TCSS port 2Tony Huang
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2. Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I2d26777e850187aee0b676de13dff915474fed7b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28mb/google/{octopus,reef}: add RO_VPD region to default FMAPMatt DeVillier
This allows for the option to persist the serial number and other device-specific information when switching from stock ChromeOS and upstream coreboot firmware images. Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-28mb/google/brya/var/crota: fix Goodix touchpadTerry Chen
- Fix Goodix hid and hid offset BUG=b:230415144 BRANCH=brya TEST=build and boot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I5a5c1cdca0cec15d65fe62a3104652d2d347fd54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28mb/google/brya: disable early EC sync for nereidPeter Marheine
The ITE EC used on Nereid can take a long time to update, and especially too long to erase. There is a 1 second timeout enforced on the EC erase command, but Nereid's IT81302 will typically take about 5 seconds to complete erase, and could take as long as 30. Since this affects any Nissa variant using an ITE EC and it's nice to make the entire Nissa project consistent, this change disables early sync for all Nissa boards. BUG=b:222987250 TEST=EC software sync is no longer attempted (and thus does not fail) on Nereid. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2022-04-27mb/google/brya/var/banshee: Update the FIVR configurationsFrank Wu
This patch enables V1p05 and Vnn external bypass VRs for Banshee. BUG=b:207116793 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Idb56890db40f90f163d8dadf5bf7c7335469771a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63860 Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27mb/google/brya/var/vell: Enable TBT PCIe root port 3Gaggery Tsai
This patch enables TBT PCIe root port 3. BUG=b:230464233 TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and ensure 07.3 is in the list. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/dedede/beadrix: Update DPTF settingTeddy Shih
Update DPTF Policy and temperature sensor values from thermal team. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I34c1298dc8412121f8688842bb8d69d7fafa46f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-27soc/intel/jasperlake: Revert CdClock settingSimon Yang
Revert CdClock setting and use default value 0xff. Previous problem was fixed by Jasperlake FSP in version 1.3.09.31, so we can use the original CdClock setting in baseboard. BUG=b:206557434 BRANCH=dedede TEST="Built and verified on magolor platform to confirm FSP solution works" Cq-Depend: chrome-internal:4662167 Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27mb/google/octopus/Kconfig: Remove space saving optionsArthur Heymans
Commit 28e61f1634 "device: Use __pci_0_00_0_config in config_of_soc()" significantly reduced the size of the bootblock. This makes the space saving options, required to make to bootblock fit in the 32K SOC limit, unnecessary. TESTED: with configs/config.google_octopus_spi_flash_console the .text size is 0x29c8 bytes which is still well below the 0x8000 SOC limit. Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/corsola: Add RO_GSCVD area to FMAPYu-Ping Wu
This area is used for storing AP RO verification data. BUG=b:229670703 TEST=emerge-corsola coreboot TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout BRANCH=none Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-04-27mb/google/nissa/var/craask Add device settingsTyler Wang
Add the configuration in device tree: 1. Add speaker codec and speaker amp settings 2. Add Elan touchscreen settings 3. Add WFC and usb settings 4 Add Elan Touchpad settings 5. Add WiFi configuration 6. Add LTE settings BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iabf7f864082714ef1fecdee984fbebf1f3f0a672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27mb/google/brya/var/craask: Add GPIO tableTyler Wang
Fill GPIO table for Craask. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27mb/google/brya/var/craask: Generate SPD ID for supported memory partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. MT62F1G32D4DR-031 WT:B MT62F512M32D2DR-031 WT:B BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27soc/intel/adl/chip.h: Rename max_dram_speed to include unitsScott Chao
The unit of dram speed is MT/s so append it on variable name. BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-27mb/google/brya/var/crota: update gpio configurationScott Chao
- enable CPU PCIe VGPIO for PEG60 - enable GPP_C3/ GPP_C4 native function - set unused GPIO to NC BUG=b:229584785 BRANCH=none TEST=build and boot into kernel v5.10 Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/brya/var/crota: enable boot from SSD/ eMMCScott Chao
- Fix eMMC reset/ enable GPIO pins. - Fix clk_req and clk_src BUG=b:229437061 BRANCH=none TEST=build and boot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/brya/var/crota: Limit dram speed to 4800 MT/sScott Chao
When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1) page 121 recommends a maximum DRAM speed of 4800 MT/s. BUG=b:229549930 BRANCH=none TEST=build and pass memory training Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I38f0006d478702afb382d30338f20b46641964ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-27mb/google/brya/var/crota: modify DQ/ DQS tableScott Chao
BUG=b:229547171 BRANCH=none TEST=pass memory training with error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If6acf8cb9474f816374743fd1e800da46958993d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-27mb/google/brya/var/vell: Fix camera LED flicker problemShon Wang
Camera LED flicker 3 times or so as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot preventing camera LED flicker. Corrects that by explicitly sequencing the reset GPIO and power GPIO BUG=b:219644184 TEST=Build and boot on vell, observe whether camera LED flickers Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27mb/google/skyrim: Configure SD_AUX_RESET_L signalIan Feng
Set native function (SD_AUX_RESET_L), and drive it high. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. 02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01) Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-27mb/google/skyrim: Include smm handlerRaul E Rangel
We need to include the SMM handler to enable SCI events when ACPI is enabled. With this enabled we now see we have EC timeout problems while in SMI: [SPEW ] SMI# #1 [WARN ] SMIx88 => 0x800 [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000 [DEBUG] Chrome EC: UHEPI supported [ERROR] Timeout waiting for EC QUERY_EVENT! [DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. [ERROR] EC returned error result code 1 [DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb We still need to debug that. I suspect we have problems reading from the ACPI IO decodes 0x62 or 0x66. BUG=none TEST=Verify SMI handler runs Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-04-27mb/google/skyrim: Fix eSPI configurationJon Murphy
* Use GPE 24 since it doesn't conflict with any existing GEVENTS. * Remove IRQ 12 mapping since it's not used. * Unmask IRQ1 in PM registers. * Use the new SMITYPE_ESPI_SCI_B SCI. BUG=b:227282870 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-25mb/google/zork: Correct PIRQ_MISC0 configurationRaul E Rangel
The current configuration is masking off IRQ 1 and IRQ 12 to the PIC. This for some reason causes problems when using level triggered interrupts. This change updates the PIRQ_MISC0 value to match what skyrim is doing. This will enable level interrupts to work correctly. BUG=b:218874489, b:160595155 TEST=Boot zork and verify keyboard still works. Boot with patch train and verify keyboard works as expected. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I46b1fd68915c6f7aa4c34cdba57d24425752bc38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25mb/google/skyrim: Prepare for enabling PSP verstageKarthikeyan Ramasubramanian
Add various verstage init functions to prepare for enable PSP verstage. BUG=None TEST=Build Skyrim BIOS image with PSP verstage enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d0dba05d4d083e2c6860078676e59cf8f487c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-24mb/google/poppy: Convert 'If (LGreater(STA,0))' to 'If (STA > 0)'Elyes HAOUAS
Change-Id: I088e514271b785e59907b0271eb89727ae1e7c05 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24mb/google/brya: Create mithrax variantJohn Su
Create the mithrax variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:223091246 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MITHRAX Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-24tpm: Allow separate handling of Google Ti50 TPMJes Klinke
A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50 to be able to take slightly different code paths, when e.g. evaluating whether TPM firmware is new enough to support certain features. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-24mainboard/google: Remove unused <boardid.h>Elyes Haouas
Found using: diff <(git grep -l '#include <boardid.h>' -- src/) <(git grep -l 'UNDEFINED_STRAPPING_ID\|BOARD_ID_UNKNOWN\|BOARD_ID_INIT\|board_id(\|ram_code(\|sku_id(' -- src/) |grep "<" Change-Id: I2611be41e8730a9b189b1b0aa3fe62be0757b371 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-22mb/google/brya/var/taniks: Configure Acoustic noise mitigationleo.chou
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:227165770 TEST=build FW and system power on. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I262ef14032e0e412c63403dbb8c8fbc6a8b03dd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-22mb/google/brya/var/taniks: Add WiFi SAR table for taniksleo.chou
Add WiFi SAR table for taniks. BUG=b:226690925 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/dewatt: Set SPI speed to 100Mhz on board version 3Rob Barnes
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 BRANCH=guybrush TEST=Build and boot to OS in Dewatt board version 3. Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on drawcia. BUG=b:223687184 TEST=emerge-dedede coreboot Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/63112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/nipperkin: Fix WLAN to GEN2 speedRob Barnes
Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing the PSP to hang when resuming from S0ix suspend. The root cause is still under investigation. Just disabling PSPP fixes the hang but causes poor PLT performance. BUG=b:228830362 BRANCH=guybrush TEST=suspend_stress_test on AC and DC Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brask/variants/moli: update overridetreeRaihow Shi
Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC. BUG=b:220039297 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-04-21mb/google/brya/var/taeko: Add WIFI SAR support for tarloJoey Peng
Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:226684990 TEST=emerge-brya coreboot Cq-Depend: chrome-internal:4676926, chrome-internal:4686953 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I9852553f5c91494db845d45a94e2566248538bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/brya/var/osiris: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brya: Create osiris variantDavid Wu
Create the osiris variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:229352299 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OSIRIS Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/google/skyrim: Update SPI settings for skyrimChris.Wang
Update SPI setting as below: Normal speed:33mhz Fast speed:66mhz Alt speed:66mz TPM speed:33mhz BUG=b:225213679 TEST=boot skyrim and verify spi settings. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Icbe4b9f4794f7e883c3819258ede809c3c8922b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-20mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%Robert Chen
Increase RFI Spread Spectrum to 6% for Vell as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:228929196 TEST=emerge-brya coreboot and pass RF test as before Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20mb/google/brya/var/brya0: configure gpio for headsetAmanda Huang
Configure GPP_R0, GPP_R1, GPP_R2 and GPP_R3 for headset function enable with ALC5682I+MAX98360. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-04-20mb/google/brya/var/brya0: Swap TPM and touchscreen I2C busAmanda Huang
Based on the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:202671753 TEST=emerge-brya coreboot Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed"Rob Barnes
This reverts commit d80d88c0fec96b2fff93db87d0c83f4c6754ae7a. Reason for revert: 100Mhz should only be enabled on DeWatt on board version >=3. Enabling it on board version 2 will cause failures. BUG=b:213403891 BRANCH=guybrush TEST=Build dewatt Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/google/brya/var/redrix: Add alias back to RP6 WWAN deviceTim Wawrzynczak
This alias name is required for the mainboard.c code to generate the appropriate power-off seqeuence for use during orderly S5 shutdown from the OS. It had been accidentally removed, but is required, so this patch adds it. BUG=b:227788351 TEST=compile Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-20mb/google/brya/var/anahera{4es}: Enable power saving for Smart CardWisley Chen
Configure the power saving pin for Smart Card. BUG=b:229356121 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20mb/google/guybrush/var/dewatt: Override SPI fast speedKenneth Chan
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 TEST=Build and boot to OS in Dewatt board version 2. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brya: Disable PCH USB2 phy power gating for felwinterSridhar Siricilla
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for felwinter board. Please refer Intel doc#723158 for more information. BUG=b:221461379, b:226020977 TEST=Verify the build for felwinter board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brask/variants/moli: update type-c setting in overridetreeRaihow Shi
Add conn1 for pch_espi and add type-c port2 for pmc_mux. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19mb/google/brask/variants/moli: add delay time to rtd3-coldRaihow Shi
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, the reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing. We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:228907551 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brask/variants/moli: remove i2c1 in overridetreeRaihow Shi
Remove i2c1 because brask devicetree is already has it. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/skyrim: Configure Pen Detect deviceIan Feng
Enable pen garage. Pen detect is active low. BUG=b:229168203 TEST:Build and boot to OS in skyrim. Evtest work as expected Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649922170.578779, -------------- SYN_REPORT ------------ Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-19mb/google/skyrim: Add Goodix touchscreenIan Feng
Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:228907558 TEST=local build and tested with Goodix touch screen Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brask: fix boot beepDtrain Hsu
Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK. BUG=b:229345416 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot and verify if the buzzer beeps. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brask/variants/moli: Pick VBT based on FW_CONFIGRaihow Shi
Pick specific VBTs for HDMI, DP, and ABSENT according to FW_CONFIG. BUG=b:220241277 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Icc8fbef1467605505459fce264697f670591c81e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63604 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brya/var/anahera{4es}: select DRIVERS_GENESYSLOGIC_GL9750Wisley Chen
select DRIVERS_GENESYSLOGIC_GL9750 to disable ASPM L0s. BUG=b:229213455 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ie89fa6c66974284063cd25ae8097db94a93326ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/63638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19mb/google/nissa: Add gpio lock pinsEric Lai
Followed the Brya series to lock the gpio pins in baseboard. Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216671701 TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that nivviks boots successfully to kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brya: Add Kconfig for TPM I2C busRaihow Shi
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:229200525 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driverTerry Chen
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:226315394 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/guybrush/var/dewatt: Update APU STT settingChris.Wang
update STT setting for dewatt. BUG=b:228040295 BRANCH=guybrush TEST=build, verify the parameter has been applied to the system by checking the AGT tool. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af Reviewed-on: https://review.coreboot.org/c/coreboot/+/63699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-18mb/google/guybrush: Remove EC_ENABLE_LID_SWITCHRob Barnes
Remove EC_ENABLE_LID_SWITCH since this causes a duplicate SW_LID entries. The other SW_LID entry is generated by MKBP. BUG=b:228907256 BRANCH=guybrush TEST=Lid open close triggers events on Nipperkin Change-Id: I5c1cf7aeac8405bce7bfc77110eceaf3e5383fe7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-18mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ssKevin Chiu
BUG=b:227296841 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass PLT criteria: S0 > 600ms, s0i3 > 14 days Change-Id: I9c61e1d0f3db8b9885040255d6de266616768b68 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-04-14mb/google/guybrush: Set BT USB to use GPIO for statusTim Van Patten
Set the BT USB device to use GPIO for the power status. This causes an ACPI `_STA()` function to be generated that returns the power status of the BT USB device, rather than always returning `0x1`. This `_STA()` function can be used during boot to skip enabling the device (and performing the associated sleep) if the device is already powered on. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa Reviewed-on: https://review.coreboot.org/c/coreboot/+/63559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14mb/google/skyrim: Inject SPDs into APCBKarthikeyan Ramasubramanian
Update the build scripts to inject variant specific SPDs into APCB. BUG=None TEST=Build and boot to OS in Skyrim boards with all the concerned memory parts. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63600 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14mb/google/skyrim/var/skyrim: Add supported memory partsKarthikeyan Ramasubramanian
Add supported memory parts and generate the associated DRAM part ID. Also for MT62F2G32D8DR-031 WT:B memory part, add a custom SPD that configures the DRAM speed at 5500 MHz. Use this custom SPD until that part can operate at full speed (i.e. 6400 MHz). BUG=None TEST=Build Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14mb/google/brya/var/kano: Configure Acoustic noise mitigationDavid Wu
Setup the following acoustic noise mitigation features: 1) Slew rate for both IA and GT domains to 1/8 2) Disable Fast package C ramp BUG=b:229046516 TEST=build and verified by power team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ifb5700391e33818878994f205acae7ee3b1b96d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-14mb/google/nipperkin: Disable PSPP for WLANRob Barnes
Disable PSPP parameters for WLAN card on Nipperkin. This feature is causing S0ix resume hangs. BUG=b:227296841,b:228830362 BRANCH=guybrush TEST=Suspend stress test passes on Nipperkin Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63593 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14mb/google/brya: Add variant_init and variant_finalize callbacksTim Wawrzynczak
Some brya variants may need to initialize and finalize some variant-specific devices during ramstage, therefore add the commonly-used hooks and callbacks to support this. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iede6dc5a5b9a7385fedd59d4eeaaba118eff0e20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-13mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_configKevin Chiu
BUG=b:228448327 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage check ACPI device "LCD" in SSDT Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I42c5abdbe3bfab72016d56399278a7aff9e33377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-13mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and DewattYu-Hsuan Hsu
We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot Nipperkin and Dewatt and then verify the devbeep and gpio values in kernel Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-13mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcntReka Norman
Configure lcnt and hcnt directly to give the required frequency, tHIGH and tLOW, instead of using rise and fall times. Aim for a frequency of 390 kHz to make sure it doesn't exceed 400 kHz on different boards. BUG=b:227517802 TEST=Probe the clock line and check that it meets the requirements for frequency, tHIGH and tLOW. Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-13mb/google/brya: Create craask variantTyler Wang
Create the craask variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASK Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-13mb/google/brya: Add missing parameter name to variant_generate_s0ix_hookReka Norman
Fixes the following build error: src/mainboard/google/brya/mainboard.c: In function 'variant_generate_s0ix_hook': src/mainboard/google/brya/mainboard.c:157:40: error: parameter name omitted void __weak variant_generate_s0ix_hook(enum s0ix_entry) ^~~~~~~~~~~~~~~ BUG=None TEST=`abuild -a -x -c max -p none -t google/brya` now succeeds Change-Id: Id578766e2a3b7647e920740dde3e356a7db39d4d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-13mb/google/brya/var/nereid: Enable OZ711LV2LN SD card controllerReka Norman
Select the Bayhub LV2 driver, and implement power sequencing as per the datasheet. BUG=b:223304542 TEST=Check that connecting an SD card works as expected in the OS. Probe the EN and RST signals and check the timing requirements are met. Change-Id: Id1cca2024e06e5b2c7cefd22aa0b735bc542dc3b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-13mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1Amanda Huang
Based on the latest schematic, change MAX98360 AMP interface from I2S2 to I2S1 due to Intel BT offload concern. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-12mb/google/brya/var/vell: add WWAN power sequence setting for vellRobert Chen
Add WWAN power sequence setting to meet spec BUG=b:220084872 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-09mb/google,samsung: Drop init_bootmode_straps()Kyösti Mälkki
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-07mb/google/brya/var/taniks: Enable Genesys L1 max entry delayJoey Peng
The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power ↵Teddy Shih
consumption To achieve low power consumption, we disable unused PCIe and SATA pins at beadrix/overridetree.cb according to baseboard/devicetree.cb and mainboard schematic. Original measured beadrix board's power consumption is about 250 mW. After we disable unused PCIe and SATA pins, as well as, enable the other low power MUX CL (3487086: USB MUX: Update low power mode of MUX anx7447 used as MUX only | https://chromium-review.googlesource.com/c/chromiumos/platform/ec/ +/3487086), the measured power consumption achieves about 110 ~ 116 mW, as well as, meets Google battery life for 14 days in the suspend state and Intel low power consumption about 116 mW. BRANCH=dedede BUG=b:204882915 TEST=on beadrix, measured power consumption meets Intel power consumption. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776 Reviewed-by: Teddy Shih <teddyshihau@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07mb/google/guybrush: allow MKBP devices and disable TBMC deviceKenneth Chan
Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:227240985 BRANCH=guybrush TEST=manual test on Dewatt: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63394 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07mb/google/brya/var/nereid: Add WLAN power sequenceReka Norman
There are currently two issues related to the WLAN power sequencing on nereid: - If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck in S3. - During warm reboot, if we only assert RST without pulling the power low, then the kernel crashes. As a workaround while we investigate these issues, we pull the EN high in S5, then actively drive it low in bootblock and high in romstage to make sure it goes low during warm reboot. BUG=b:227694137, b:225261075 TEST=Cold boot succeeds, and there's no kernel crash during warm reboot. Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07mb/google/brya/var/nereid: Enable pen garageReka Norman
BUG=None TEST=evtest works: Select the device event number [0-14]: 9 Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153020.275201, -------------- SYN_REPORT ------------ Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153025.848689, -------------- SYN_REPORT ------------ Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153028.383195, -------------- SYN_REPORT ------------ Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153080.869155, -------------- SYN_REPORT ------------ Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-07mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMIReka Norman
Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" The default value before updating the descriptor is Type-C, but this was chosen arbitrarily. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-06mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD deviceChris.Wang
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim, clock source 0/1/2 are routed for WLAN/SD/SSD device. BUG=b:227297986 BRANCH=none TEST=Build Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06mb/google/brya: Enable dynamic debug capability for brya familySridhar Siricilla
The patch enables dynamic debug capability for Brya family of boards. BRANCH=MAIN BUG=b:153410586 TEST= Verified the CSE firmware update functionality on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-04-06drivers/intel/fsp1_1: Rename hob finding functionsArthur Heymans
The hob finding functions are never looped over so there is no point for the 'next' inside their name. Change-Id: I18e452d313612ba14edda479d43f2797f6c84034 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06ChromeOS: Drop filling ECFW_RW/RO state in CNVSKyösti Mälkki
This field was never meant to be filled out by coreboot, because it can't know what the right value for this will be by the time the OS is running, so anything coreboot could fill in here is premature. This field is only read by the chromeos-specific `crossystem` utility, not by kernel code, so if one does not run through depthcharge there'll be many more broken assumptions in CNVS anyway. Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Add legacy mainboard_ec_running_ro()Kyösti Mälkki
Motivation is to have mainboard_chromeos_acpi_generate() do nothing else than fill ACPI \OIPG package. Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-05mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD dataChris.Wang
The value at offset 329 should be: 0x4B -> "K" not 0x48 -> "H" in ASCII code. BUG=b:224884904 TEST=Build, confirm the part number is matched the corresponding parts Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05mb/google/guybrush/var/dewatt: Override SPD file for Samsung partsRobert Zieba
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This commit overrides the default SPD files used for these parts BUG=b:224884904 TEST=Verified that Dewatt SKU1 and SKU3 boot with changes Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-04mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHzEddy Lu
Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz. BUG=b:207333035 BRANCH=none TEST=built and verified adjusted I2C speed around 1MHz Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63241 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02mb/google/skyrim: Fix ESPI communication issuesKarthikeyan Ramasubramanian
* Use dedicated ALERT pin to resolve NO_RESPONSE error/status while getting target configuration. * Configure the ESPI to operate at 16 MHZ since operating at 33 MHz causes boot stall. BUG=b:226635441 TEST=Build and Boot to OS in Skyrim. Ensure that EC <-> AP communication is working fine through Host Command debug logs in EC console, ectool version command. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/63286 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02herobrine: fix emmc and sd card clocksShelley Chen
Found an issue where emmc and sd clocks were being misconfigured due to using incorrect integer values when called instead of the defined enums. Fixing by splitting the clock_configure_sdcc() function into two (sdcc1 and sdcc2) as there was no commonality between the two cases anyway. As a result, we can also get rid of the clk_sdcc enum. BUG=b:198627043 BRANCH=None TEST=build herobrine image and test in conjunction with CB:63289 make sure assert is not thrown. Change-Id: I68f9167499ede057922135623a4b04202f4da9b5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-01mb/google/guybrush: Remove elog_gsmi_cb_mainboard_log_wake_sourceRob Barnes
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes eSPI transactions. If the SMI interrupts an ongoing eSPI transaction from the OS it will conflict and cause failures. Removing this call to avoid conflicts. This can be re-enabled after refactoring google_chromeec_get_mask to use ACPI MMIO. BUG=b:227163985 BRANCH=gubyrush TEST=No 164 errors detected during suspend_stress_test /sys/firmware/log output after resume before change: SMI# #1 ELOG: Event(B0) added with size 9 at 2022-03-31 19:52:51 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:52:51 UTC Chrome EC: clear events_b mask to 0x0000000000000000 after change: SMI# #6 ELOG: Event(B0) added with size 9 at 2022-03-31 19:50:19 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:50:19 UTC Change-Id: I3320e3fb8bd9e9e0db84332e1d147a0af25f7601 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63280 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/google/brya/var/nereid: Add separate VBT for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Cq-Depend: chrome-internal:4650256 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6a90d3d86b32f73ec0130e582539d1c5b045da62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01mb/google/brya/var/nereid: Disable C1 PMC mux conn for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I039c30f95d959dba489b24b6938d08da937c5e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 15:26:39 +0000