mb/google,samsung: Drop init_bootmode_straps()

Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

3 files changed, 4 insertions, 90 deletions

diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index 227e595db1..0e0189549e 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/pci_ops.h>
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <device/device.h>
@@ -10,9 +9,6 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
-#define FLAG_SPI_WP	0
-#define FLAG_REC_MODE	1
-
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
@@ -25,44 +21,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
-static bool raw_write_protect_state(void)
-{
-	return get_gpio(GPIO_SPI_WP);
-}
-
-static bool raw_recovery_mode_switch(void)
-{
-	return !get_gpio(GPIO_REC_MODE);
-}
-
 int get_write_protect_state(void)
 {
-	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-	return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
+	return get_gpio(GPIO_SPI_WP);
 }
 
 int get_recovery_mode_switch(void)
 {
-	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-	return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
-}
-
-void init_bootmode_straps(void)
-{
-	u32 flags = 0;
-	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-
-	/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
-	if (raw_write_protect_state())
-		flags |= (1 << FLAG_SPI_WP);
-
-	/* Recovery: GPIO12 = RECOVERY_L, active low */
-	if (raw_recovery_mode_switch())
-		flags |= (1 << FLAG_REC_MODE);
-
-	/* Developer: Virtual */
-
-	pci_s_write_config32(dev, SATA_SP, flags);
+	return !get_gpio(GPIO_REC_MODE);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index d8ecb4e652..563e32b79c 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -6,15 +6,10 @@
 #include <device/device.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <ec/google/chromeec/ec.h>
 #include <soc/chromeos.h>
-#include <soc/sata.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "onboard.h"
 
-#define FLAG_SPI_WP	0
-#define FLAG_REC_MODE	1
-
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
@@ -27,44 +22,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
-static bool raw_write_protect_state(void)
-{
-	return get_gpio(GPIO_SPI_WP);
-}
-
-static bool raw_recovery_mode_switch(void)
-{
-	return !get_gpio(GPIO_REC_MODE);
-}
-
 int get_write_protect_state(void)
 {
-	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-	return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
+	return get_gpio(GPIO_SPI_WP);
 }
 
 int get_recovery_mode_switch(void)
 {
-	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-	return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
-}
-
-void init_bootmode_straps(void)
-{
-	u32 flags = 0;
-	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-
-	/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
-	if (raw_write_protect_state())
-		flags |= (1 << FLAG_SPI_WP);
-
-	/* Recovery: GPIO12 = RECOVERY_L, active low */
-	if (raw_recovery_mode_switch())
-		flags |= (1 << FLAG_REC_MODE);
-
-	/* Developer: Virtual */
-
-	pci_s_write_config32(dev, SATA_SP, flags);
+	return !get_gpio(GPIO_REC_MODE);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
deleted file mode 100644
index 5c978baabb..0000000000
--- a/src/mainboard/google/jecht/romstage.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootmode.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8772f/it8772f.h>
-#include "onboard.h"
-
-void mainboard_post_raminit(const int s3resume)
-{
-	if (CONFIG(CHROMEOS))
-		init_bootmode_straps();
-}