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Adapted from Chromium commit 9522225e
[Kefka: Add memory SPD info for Hynix H9CCNNN8GTALAR-NUD]
Add current available ram_id to support Hynix H9CCNNN8GTALAR-NUD spd info.
RAM_ID: 0110 4GiB Hynix H9CCNNN8GTALAR-NUD
RAM_ID: 0111 2GiB Hynix H9CCNNN8GTALAR-NUD
Original-Change-Id: I48386ff3e5f80de94ea87359a09a5ec2577043b5
Original-Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/664517
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0ae76c4d8313246927bbc3f71b21f3611c89a6e3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update Eve's VBT from v211 to v221, and change the backlight
control type from PWM to VESA eDP/AUX. This allows the OS to
select the proper backlight control type for the panel.
Test: Eve backlight control now functional under Windows 10
(Linux requires some pending patches to fix)
Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In https://review.coreboot.org/c/coreboot/+/37459
(commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset
pin control of FPMCU to var/board/ramstage, but does not implement it for
dratini/jinlon. So, add it in dratini/jinlon.
BUG=b:146366921
TEST=emerge-hatch coreboot
Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The change applies the DPTF parameters received from the thermal team.
BUG=b:146540028
TEST=build and verified by thermal team.
Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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add new SKU ID below:
19 - Garg PVT (HDMI DB, Touch)
20 - Garg PVT (2A2C DB, Touch)
38 - Garg360 EVT (2A2C DB, touch, no stylues, rear camera)
BUG=b:146260545
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: Ic74ce14db7060f3124c1a277eb3625ce0ff0b9f0
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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BUG=b:144809606,142094759
BRANCH=none
TEST=none
Change-Id: Iae20d2262c910044dde84f10d795f4aee3318532
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Signed-off-by: Kangheui Won <khwon@chromium.org>
Co-Author: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37925
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow MEM_STRAP_* comment style to be consistent with other boards.
BUG=b:144809606
BRANCH=hatch
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I4945f676f307af9b8c0baa1fbcaf33113de647c3
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This
toggles the MAX amp which not all boards have. Move the pin
configuration to boards with the respective devicetree configuration
following on from the theme of commit b417786525.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_C15 group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_A* group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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To be safe for now, don't differentiate between SKUs and use lower
values to ensure board won't be browned out.
BUG=b:143246320
TEST=none
BRANCH=none
Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37651
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generally work towards a more loose baseboard definition by moving out
some original assumptions to be board specifics. Specifically Puff does
not have the MAX98357A speaker amp and enabling the driver winds up
generating incorrect SSDT tables that confuse the kernel. Since
devicetree inherits the chip from device node in base and an override
will also inherit the chip and thus dispatch the unwanted fill_ssdt fn
call.
V.2: lean on linker to drop max98357a driver when not in dt.
BRANCH=none
BUG=b:146519004
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37909
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable PCH HDA and configure dmic+ssp registers.
BRANCH=none
BUG=b:146519004
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: If9495261201ca256cdb35352338c0b3a82a50196
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Two things here:
i. ) FSP requires that function 0 be enabled whenever any non-zero
functions hang under the same bus:device.
ii.) FSP reorders function 6 RP to be function 0 if function 0 is
indeed unused.
BUG=b:146437819
BRANCH=none
TEST=none
Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Before tuning i2c frequency,
I2C0: 479.4 KHz
I2C1: 491.4 KHz
I2C4: 476.4 KHz
After tuning i2c frequency,
I2C0: 391.8 KHz
I2C1: 396.4 KHz
I2C4: 388.8 KHz
BUG=b:146535585
BRANCH=hatch
TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: I55d095efb60eba4e860b54bb90e8e0df62d88419
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37831
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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jinlon supports LTE, so remove WWAN_RESET NC configuration
BUG=none
TEST=emerge-hatch coreboot
Change-Id: Ibc5d21f0a33952f519265a5ce2df559a79346d9e
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37837
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adding extra USB configuration since Puff has different USB ports compared to hatch
BRANCH=none
BUG=b:146437609
TEST=none
Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Missing bus init for RTL8111H ethernet chip hanging on bus.
V.2: Include admendments from Kangheui.
BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Seems nothing special is needed here from coreboot.
V.2: Fix typo as well in speed map.
BRANCH=none
BUG=b:143047058
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ief750f98677b2017af78fb0b5bc98e1492dedbe4
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Drallion only supports on board dimm. Remove the spd read from
SMBus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.
BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37780
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drallion supports D3 hot not D3 cold. Remove the code which used
for Wilco 1.0 CML.
BUG=b:140068267
TEST=boot into OS without any issues
BRANCH=none
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifc83fae7ac462d3e6595742d96952c2a2607c88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Mike Wiitala <mwiitala@google.com>
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Create initial overlays and build for mushu
Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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enable eMMC in puff/overridetree.cb
BRANCH=none
BUG=b:146455177
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Change-Id: I4dcdcb734e20830ac97d4a826de61017afc6ee67
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I4cd9d22d2105c270a3d1e8a0be40b594c7c8b226
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37687
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If99c8ea1aa437f261e8ab3c8a164d01be8bc58e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37271
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not
enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized),
which indicates the TEVT method is empty.
The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses
this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT.
The TEVT method will be removed from the ASL code when the EC does not support TEVT.
BUG=N/A
TEST=Tested on facebook monolith.
Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Add VBTs for all rambi variants, extracted from VGA BIOS
from stock firmware images using intelvbttool.
Test: boot several rambi variants using MrChromebox edk2/master
branch with Baytrail GOP driver and extracted VBTs.
Change-Id: I401ae5accd852fc5211092a5944fc85871b642ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add VBTs for jecht variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy.
Use a common VBT for all except tidus, since it differs
from the others.
Change-Id: I570bdb749ef7d49f41539074220bb16c9c100342
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This impacts boards:
hatch (&variants) and drallion.
Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.
Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.
BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Add VBTs for beltino variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy. Use
a common VBT for all except monroe, since it differs as
it has a built-in display (being a Chromebase vs Chromebox).
Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update VBT using file extracted from VGA BIOS from stock
firmware image using intelvbttool, zero-padded to 0x11ff
bytes to make the Intel BMP editor happy.
Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add VBTs for all auron variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy.
Test: boot several auron variants with libgfxinit and Tianocore
payload, ensure both internal and external displays as well as
HDMI audio function properly under Linux (4.x/5.x).
Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove the sarien_cml and arcada_cml subdirectories from the
drallion/variants directory.
BUG=b:140068267
TEST=./build_packages --board=drallion
Confirm that drallion still builds successfully.
BRANCH=none
Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f
Signed-off-by: Mike Wiitala <mwiitala@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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BRANCH=none
BUG=b:146172098
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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On nocturne, the VBT specifies that the native panel resolution
(3000x2000) is to be used by FSP/GOP init, which makes payload
and grub menus extremely difficult to read. Change the default
POST resolution specified by the VBT to 1500x1000 instead
(200% scaling) which is much more legible.
Test: build/boot nocturne with GOP init and Tianocore payload,
observe menu text is actually readable.
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I767a2b8319c7673e3460acfad534140409bf1d57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Confirmed with Goodix team, so increase reset delay time
from 120ms to 150ms.
BUG=b:144267684
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I4ff95ac89314fc031620ca28e4f6e6e26cdef3f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37544
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. SKU ID 1 and 3 for eMMC
2. SKU ID 2 and 4 for SSD
BUG=b:144815890
BRANCH=firmware-hatch-12672.B
TEST=FW_NAME="akemi" emerge-hatch coreboot
chromeos-bootimage
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I25f0c4142be024ba55f671491601d1f6ec26d68a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37498
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Change-Id: Ibe2d92990d0074266aa05ada749e9dad55e609a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
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Add package and APU selections to mainboards and remove symbols no
longer used in soc//stoneyridge.
Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Make a new Kconfig symbol for using soc//stoneyridge. This code also
supports Prairie Falcon is backward-compatible with Carrizo and Merlin
Falcon.
Although Bettong uses Carrizo, it does not currently rely on stoneyridge
source, so it is unaffected by this change.
Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37537
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.
How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.
Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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Tuning i2c frequency for dratini:
I2C0: 396 KHz
I2C1: 398 KHz
I2C3: unused
I2C4: 394 KHz
BUG=b:145891557
BRANCH=hatch
TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: I1431554fbce5f3ce113ef1a934e39448e7ba321c
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37605
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow thermal table for first tuning.
BUG=b:144464314
TEST=Built and tested on drallion
Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36860
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Change-Id: If40fa38e5b249452a6dacf4a4045b6bd00c27cfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change sets TCC offset to 10 for kohaku.
BUG=b:144532818
BRANCH=firmware-hatch-12672.B
TEST=Checked thermal and performance efficiency internally (b:144532818)
Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Grace Kao <grace.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit creates a foob variant for Octopus. The initial settings
override the baseboard was copied from variant phaser.
BUG=b:144890301
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ibcdda4dd0846612f5e98ab454db7144c1caf0507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37456
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the SMBIOS system type to detachable for nocturne and
soraka variants, to allow the OS to correctly process events.
Change-Id: Ie0ee5ea6666542c0bca2c264b2ed2e6135b78658
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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1. No gpio control in bootblock
2. Disable power and assert reset in ramstage gpio
3. Power on and then deassert reset at the end of ramstage gpio
4. Disable power and assert reset when entering S5
On "reboot", the amount of time the power is disabled for is
equivalent to the amount of time between triggering #4 and wrapping
around to #3, which is about 400ms on Kohaku.
Since #2 forces power off for FPMCU, S3 resume will still
not work properly.
Additionally, we must ensure that GPP_A12 is reconfigured as an output
before going to any sleep state, since user space could have configured
it to use its native3 function.
See https://review.coreboot.org/c/coreboot/+/32111 for more detail.
The control signals have been validated on a Kohaku in
the following scenarios:
1. Cold startup
2. Issuing a "reboot" command
3. Issuing a "halt -p" and powering back on within 10 seconds
4. Issuing a "halt -p" and powering back on after 10 seconds
5. Entering and leaving S3 (does not work properly)
6. Entering and leaving S0iX
BRANCH=hatch
BUG=b/142751685
TEST=Verify all signals as mentioned above
TEST=reboot
flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin
TEST=halt -p
# power back on within 10 seconds
flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin
TEST=halt -p
# power back on after 10 seconds
flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin
Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This removes the weakly linked function to configure the SPI lockdown.
Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This reverts commit 0bc35af93326ec3232ec73c9b1334241b85f0252.
Reason for revert: This change breaks runtime s0ix.
BRANCH=hatch
BUG=b:141831197
TEST=Check slp_s0 residency increased when system is idle.
Change-Id: Ida80f55b56de7129ed629eb29bd14f2ef300126f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Create new variant for Lick that is copied from phaser variant.
Remove unnecessary code, due to not support touchscreen and stylus.
Set to default_override_table.
Remove variant.c.
BUG=b:145181137
BRANCH=octopus
TEST=./util/abuild/abuild -p none -t google/octopus -x -a
Change-Id: If732d94194defb9f5ee9c847ee93dd58aef01174
Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37247
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After adjustment on Drallion
Touch Pad CLK: 393 KHz
Touch Screen CLK: 381 KHz
H1 CLK: 391 KHz
BUG=b:144245601
BRANCH=master
TEST=emerge-drallion coreboot chromeos-bootimage
measure by scope with drallion.
Change-Id: Id669d7199bc6ed4b55d7542f095c6c8baf00f984
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37230
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All serial I2C bus frequencies should not be over 400KHz in kohaku,
but the measurement showed frequencies of I2C1 and I2C4 were over
400KHz. (b:144885961)
This change adjusts I2C speed settings to limit that frequencies to
400KHz.
The new setting values have been from other projects using same I2C
components, and verified I2C1 and I2C4 frequencies < 400MHz internally.
BUG=b:144885961
BRANCH=firmware-hatch-12672.B
TEST=Verified I2C1 and I2C4 frequency not over 400KHz
Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Tune DPTF to ensure compliance with Akemi thermal design
requirements
BUG=b:144195069
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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(Auto-Generated by create_coreboot_variant.sh version 1.0.0).
BUG=b:145101696
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_STRYKE
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:144002424
TEST=Ensured no TPM time out issue and system can boot to OS
Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Enable ACPI methods to control privacy screen on Drallion devices.
Drallion devices may not have a privacy screen and it is up to the
EC to determine if the privacy screen is present on the system.
BUG=b:142656363
TEST=emerge-drallion coreboot chromeos-bootimage
Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36045
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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configuration
The methods generally tested OP region settings and only changed them if
they were not in their desired values. Instead, assign them directly
without checking them.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The mutex is only used in one method and that method is serialised. Remove
the mutex.
BUG=chromium:959232
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36745
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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In particular:
- Set voltage before enabling regulators
- Enable regulators and the clock without any sleeping in between. There's
no need to wait there.
- Sleep 1 ms in order to wait for regulator voltages settling before
lifting xshutdown.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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In particular:
- Enable regulators *after* configuring the voltage
- Allow 1 ms for the voltages to settle
- Enable clock after powering on regulators
- Remove extra delays between enabling things. The sensor requires 8192
clock cycles after the reset is lifted before I²C access, so 1 ms is
enough.
- Make the delay after lifting xshutdown 10 ms. This guarantees that
streaming will only start once the sensor has had enough time to settle
after lifting the reset.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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The PMIC opregion is used to change the direction of two GPIOs for I²C
daisy chain operation. Do this after the PMIC is powered on, not before.
BUG=chromium:959232
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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The pull direction is used to determine the initial state of the pin. If
no pull direction is specified, the pin will remain as input. Fix this.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I1158bc8aaa447b223e8ce25d808348e758de28c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify DPTF parameters.
BUG=b:131272830
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I93930525edf4c5efb6b73bdfc8f16950754f7c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37272
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When migrating glados (and variants) to FSP 2.0, the older board-
specific VBTs were dropped in favor of the default FSP 2.0 VBT due to
compatibility issues. Now that libgfxinit is available and the default,
restore the board-specific VBTs so that external displays function
properly. Select MAINBOARD_NO_FSP_GOP for all variants except glados
since FSP/GOP init will not function properly with the older VBTs.
Test: build/boot chell and caroline variants w/libgfxinit, verify
external displays now work again.
Change-Id: If55a67e0d3d78e4acf80cee1733ad8e14b8847d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add libgfxinit support for rammus. Use panel init values from VBT.
Test: build/boot rammus with libgfxinit and Tianocore payload
Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add VBT files for Atlas, Nocturne, Rammus, and Soraka variants.
Extracted from ChromeOS recovery images for the respective boards.
Select INTEL_GMA_HAVE_VBT for all variants except Poppy, since
it doesn't have a VBT (or a recovery image from which to extract one).
Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add G2 GTCH7503 HID TS support
spec from G2: G7500 / Ver.1.2 (3, April, 2018)
BUG=b:141577276
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I91e4f2b934b64b14bca20108037b721288d40942
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37318
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Builds that would otherwise be reproducible are sometimes
broken due to added #include combined with __LINE__ used
in assert() statement.
Change-Id: If4a02393799a34bbae4f6e506052774526c1a969
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37266
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic92e08ae5b741889a8200d10ea8148e4b4384dc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37270
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add ELAN EKTH6918 USI touchsreen support.
BUG=b:131205495 b:127996093
TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage
and check touchscreen work.
Change-Id: I8b003685cd7ee68738bcd4298b63a44d6e6118e4
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37236
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Workaround to disable USB2 PHY power gating to fix issue seen when
Apple 87W USB-C charger is connected in S0ix state on WHL platforms
(based on Intel's recommendation). Issue is seen on CML platforms also.
So, disable power gating for Drallion too.
Add devicetree entry to set the flag to disable USB2 PHY power gating
for different CNL PCH based platforms
BUG=b:133775942
TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if
the system wakes up after that
Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com>
Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on Guado variant
Change-Id: Ie3a42d1d69d11eebda25e60572f5d9a7452144c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Tested on Zako variant
Change-Id: I433863b34731584797456eee6c2d270868a4f13f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Id9d9d804dfc2301b8d2186aff7be331d5ddbf18a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Idd7bfa4a97770f525c3f25f04f90c4bf092e4ae1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Both linear framebuffer and vga text mode verified
on chell and caroline variants
Change-Id: I106e7bb761055581634176a112816be8447e6745
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Now that the EC software sync in romstage ("early EC sync") patches
have landed, it's time to enable this for Hatch.
BUG=none
BRANCH=hatch
TEST=verify EC sync runs in romstage
Change-Id: Ie567ab081b95b2302b051812fbf46e183c76bab6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37025
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Meep was just the first one to fail, but the others aren't any better.
Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37163
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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According to SI team request, need to tune I2C bus 2 data
hold time more than 300ns
BUG=b:144736027
TEST=build firmware and measure I2C bus 2 data hold time
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Idc58a595c77eba8544f27682a284be6aac5dbe25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36945
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding
explicit configuration for Kohaku in the event that MEM_STRAP is set
differently in the baseboard gpio file.
BUG=b:144895517
BRANCH=hatch
TEST=None
./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pull in all copies of smm_relocation_params structs defined
for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create new variant for jinlon
BUG=b:144150654
TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto
board
Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This board never really existed and nobody has any hardware left over
for it.
Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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By removing this code, we get approximately back to
where the board was before the fmap cache feature
was added, which is small enough for the Chromium OS
default configuration for the board to fit into the
32KB that the bootblock can use on the chipset again.
Change-Id: I52c0c30a14929913ded144bf086c12938e9c2699
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid
probing by the MRC. We can do that for all boards instead, based on the
devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Only set LPC decode bits that the generic PCH code doesn't set yet. And
don't enable the IOAPIC, which is already done by generic code.
Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.
Enabling the console will be done in a followup patch.
Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This also changes the name to mainboard_pch_lpc_setup to better
reflect that it is an optional mainboard hook.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This also changes the name to mainboard_late_rcba_config to better
reflect what it does.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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