Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

10 files changed, 30 insertions, 30 deletions

diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index f218f3f31b..0173064b10 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -147,16 +147,16 @@ static void mainboard_init(void *chip_info)
 	pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
 
 	/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
-	clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
-			GPP_CLK2_REQ_MAP_MASK,
-			GPP_CLK2_REQ_MAP_CLK_REQ2 <<
-			GPP_CLK2_REQ_MAP_SHIFT);
+	clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
+		     GPP_CLK2_REQ_MAP_MASK,
+		     GPP_CLK2_REQ_MAP_CLK_REQ2 <<
+		     GPP_CLK2_REQ_MAP_SHIFT);
 
 	/* Same for the WiFi */
-	clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
-			GPP_CLK0_REQ_MAP_MASK,
-			GPP_CLK0_REQ_MAP_CLK_REQ0 <<
-			GPP_CLK0_REQ_MAP_SHIFT);
+	clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
+		     GPP_CLK0_REQ_MAP_MASK,
+		     GPP_CLK0_REQ_MAP_CLK_REQ0 <<
+		     GPP_CLK0_REQ_MAP_SHIFT);
 }
 
 /*************************************************
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index 3e9f9fad7b..7fa47bbcb5 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -61,9 +61,9 @@ static void set_clock_sources(void)
 	clock_configure_irregular_source(host1x, PLLP, 408000, 4);
 
 	/* Use PLLD_OUT0 as clock source for disp1 */
-	clrsetbits_le32(&clk_rst->clk_src_disp1,
-			CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
-			2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
+	clrsetbits32(&clk_rst->clk_src_disp1,
+		     CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
+		     2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
 
 }
 
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
index 9c4e943ae5..115f73aa1e 100644
--- a/src/mainboard/google/nyan_big/mainboard.c
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -61,9 +61,9 @@ static void set_clock_sources(void)
 	clock_configure_irregular_source(host1x, PLLP, 408000, 4);
 
 	/* Use PLLD_OUT0 as clock source for disp1 */
-	clrsetbits_le32(&clk_rst->clk_src_disp1,
-			CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
-			2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
+	clrsetbits32(&clk_rst->clk_src_disp1,
+		     CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
+		     2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
 
 }
 
diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c
index 7f8abab119..d57ac8bdd8 100644
--- a/src/mainboard/google/nyan_blaze/mainboard.c
+++ b/src/mainboard/google/nyan_blaze/mainboard.c
@@ -61,9 +61,9 @@ static void set_clock_sources(void)
 	clock_configure_irregular_source(host1x, PLLP, 408000, 4);
 
 	/* Use PLLD_OUT0 as clock source for disp1 */
-	clrsetbits_le32(&clk_rst->clk_src_disp1,
-			CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
-			2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
+	clrsetbits32(&clk_rst->clk_src_disp1,
+		     CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
+		     2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
 
 }
 
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 89169ef0bf..73e50fda63 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -42,9 +42,9 @@ static void nor_set_gpio_pinmux(void)
 	 * 3: 16mA
 	 */
 	/* EINT4: 0x10005B20[14:13] */
-	clrsetbits_le16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
+	clrsetbits16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
 	/* EINT5~EINT9: 0x10005B30[2:1] */
-	clrsetbits_le16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
+	clrsetbits16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
 
 	gpio_set_pull(GPIO(EINT4), GPIO_PULL_ENABLE, GPIO_PULL_UP);
 	gpio_set_pull(GPIO(EINT5), GPIO_PULL_ENABLE, GPIO_PULL_UP);
@@ -64,7 +64,7 @@ static void nor_set_gpio_pinmux(void)
 void bootblock_mainboard_early_init(void)
 {
 	/* Clear UART0 power down signal */
-	clrbits_le32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN);
+	clrbits32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN);
 }
 
 void bootblock_mainboard_init(void)
diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c
index f143bf9171..18b22c13ce 100644
--- a/src/mainboard/google/storm/cdp.c
+++ b/src/mainboard/google/storm/cdp.c
@@ -68,6 +68,6 @@ void board_nand_init(void)
 	configure_nand_gpio();
 
 	/* NAND Flash is connected to CS0 */
-	clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK,
-			CS0_CFG_SERIAL_FLASH_DEVICE);
+	clrsetbits32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK,
+		     CS0_CFG_SERIAL_FLASH_DEVICE);
 }
diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c
index ce03ce1421..42af265cd9 100644
--- a/src/mainboard/google/trogdor/mainboard.c
+++ b/src/mainboard/google/trogdor/mainboard.c
@@ -13,9 +13,9 @@
  * GNU General Public License for more details.
  */
 
-#include <device/device.h>
 #include <bootblock_common.h>
-#include <arch/mmio.h>
+#include <device/device.h>
+#include <device/mmio.h>
 #include <gpio.h>
 #include <timestamp.h>
 
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
index 80fe7e8266..ad5e70944c 100644
--- a/src/mainboard/google/veyron/bootblock.c
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -42,8 +42,8 @@ void bootblock_mainboard_init(void)
 		reboot_from_watchdog();
 
 	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+	setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+	setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
 	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
 	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
 
diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c
index 1107b1a6a4..ec55f7e452 100644
--- a/src/mainboard/google/veyron_mickey/bootblock.c
+++ b/src/mainboard/google/veyron_mickey/bootblock.c
@@ -44,8 +44,8 @@ void bootblock_mainboard_init(void)
 	gpio_output(GPIO(7, A, 0), 1);	/* Power LED */
 
 	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+	setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+	setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
 	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
 	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
 
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index 91396b0074..2379ae2478 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -48,8 +48,8 @@ void bootblock_mainboard_init(void)
 	gpio_output(GPIO(7, B, 7), 1);	/* LED_ERROR */
 
 	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
-	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
-	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+	setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+	setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
 	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
 	i2c_init(CONFIG_PMIC_BUS, 400*KHz);