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Adjust settings as recommended by thermal team.
Set PL1 max value tdp_pl1_override from 28W to 33W.
PL2, PL4 remain the same as CPU default.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust settings as recommended by thermal team.
Set tcc_offset value to 5 in devicetree.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:308704811#comment4.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch tries to simplify the baseboard/variant GPIO programming
for Google/Trulo. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.
With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.
BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant)
TEST=Able to build google/orisa.
Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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* Introduce a null check before calling `gpio_padbased_override`
in `variant_configure_pads`.
* This prevents potential errors in cases where the
`variant_gpio_override_table` function returns a null pointer,
indicating that there are no override pads to configure.
BUG=b:334826281
TEST=Able to avoid hang incase there is no GPIO override.
Change-Id: I733210a08091b37eda6e6b0d6924aafd5e7e6280
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82628
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Type-C kernel driver no longer programs the AP mux, as of
https://review.coreboot.org/c/coreboot/+/82077. So remove device
references to the TCSS Mux control device from the Type-C port driver.
This eliminates the following kernel error which was observed as a
result of the kernel trying to program muxes it no longer has control
over:
[ 4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95
[ 4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95
BUG=b:341331428
TEST=Run system reboot; configure mux kernel errors no longer seen.
Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1) Add all changes needed for early graphics
2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa
The InnoLux (N156HCN-EBA C7) panel is used for the device tree.
BUG=b:296433986
TEST=On-screen text message seen during MRC training on Craask
Logs:
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
[SPEW ] bootmode is set to: 0
[0.171409] DP PHY mode status not complete
[0.175509] DP PHY mode status not complete
[0.179799] DP PHY mode status not complete
[0.184087] DP PHY mode status not complete
[0.188376] DP PHY mode status not complete
[0.192665] DP PHY mode status not complete
[0.196954] DP PHY mode status not complete
[0.201243] DP PHY mode status not complete
[0.205532] DP PHY mode status not complete
[0.209821] DP PHY mode status not complete
[0.214110] DP PHY mode status not complete
[0.218397] DP PHY mode status not complete
[INFO ] Informing user on-display of memory training.
Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Micron part MT62F512M32D2DR-031 WT:B only for Orisa.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
BUG=b:337178014
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I559ed817250c40795e6c613794d4f65c636f5fc5
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82586
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 7088257b1ab715e93506619727e3bf589ea688fb.
Reason for revert: Intel suggest is NC only.
No need to change anything that isn't broken.
Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82572
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit f867c9c5473156617691d78350c362cd993bfcdd.
The new verb table breaks external mic detection on brox.
Revert and use old verb tables instead.
BUG=b:330433089
BRANCH=main
TEST=Verified headset on Brox
When connected to audiojack in power_save state of legacy hda driver,
headset is detected and audio is resumed.
Change-Id: I0d8c092de6166b2c62f5ecc3deaf4960128e6106
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82273
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Nova will use SOLDERDOWN. Add memory.c to override baseboard.
Update dram id table for correct platform parameter.
BUG=b:328711879
Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On GreenbayPOC, HDA Codec used is ALC236, different with Brox (ALC256)
Update to Realtek provided verb table for ALC236 audio codec.
BUG=b:336967284
TEST=Verified headset and audio workable on DUT with "rec" and
"aplay" command.
Change-Id: I9fbe57a0acab20387754f6b6cb5705e34c1c149b
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82413
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add devicetree settings per the schematic.
Differences to gladios:
1. remove SD reader
2. remove EMMC setting
3. modify USB port distribution
FRONT
-------------------------------------------------------
| A3 A1 |
| C0 A2 A0 |
-------------------------------------------------------
BACK
-------------------------------------------------------
| --------------- |
| | TX25A | |
-------------------------------------------------------
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81447
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Remove unused setting for retimer.
BUG=b:328711879
Change-Id: I48d8680d43a07aa3408dfbf5b25b568c2b51b343
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes VPU enablement code that is no longer needed because
the VPU is already enabled by default in the baseboard devicetree.
BUG=b:332488817
TEST=Able to see VPU PCI device in lspci list after booting
google/screebo to OS
Change-Id: I94de92e970be1548068ed4e19309a95129f041ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82423
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch enables the Versatile Processing Unit (VPU) by default for
Rex/Ovis baseboard. VPU is a dedicated AI engine that is included in
the 14th generation "Meteor Lake" Core processors.
The VPU is designed to efficiently run AI models directly on the
system on chip (SoC). There is no power regression observed while
keeping the VPU default enabled to run AI models natively hence, this
patch enables the VPU by default.
BUG=b:332488817
TEST=Able to see VPU PCI device in lspci (0:11:0) list after booting
google/screebo to OS.
Change-Id: I8b3521c8ec613b002f971eaf9d346927fe8cd656
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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There is no direct way to override CPU default power_limits for
different SKUs.
This CL add structure variant_get_soc_power_limit_config() for
variants to define and configure the values of soc_power_limits_config
for current CPU SKU.
Variants can override these values i.e. pl1, pl2, psyspl2
in variant_devtree_update().
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
check overrides setting
Change-Id: Ib60fa4e3fc502d0aeb0c94ad46ba5a55b4dd027c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82199
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematic to update the gpio table.
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I3d01e3b9eaef72d9e143f5163ee49d8c8f455b5f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82412
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the orisa variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:337178014
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ORISA
Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.
Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add stop pin control for G2 touchscreen refer to
G7500_Datasheet_Ver.1.2.
BUG=b:335803573
TEST=build and verified touchscreen works normally
Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copy the data.vbt from brox to greenbayupoc
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematics GREENBAY_0412.SCH update the gpio and
devicetree settings.
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Cq-Depend:chrome-internal:7218819
Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01.
BUG=b:339756281
TEST=Build and check Focal touchpad can work.
Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix
H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these
parts.
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
H54G46CYRBX267 0 (0000)
BUG=b:337173071
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I3aa669042908b92d7b270df077a352e197071780
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT
for riven as it has a VBT file now.
The VBT file is copied from the nivviks reference board.
BUG=b:337169542
TEST=build pass
Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable c1 state auto-demotion support for brox
BUG=None
BRANCH=None
TEST=Boot brox and verify in fsp debug logs
Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previous CL misspelling VR domain to IA not GT which cause
FVM Itrip(GT) not set correctly.
This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT)
has set to 54.
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
check overrides setting
IccLimit[1] = 216 ( 1/4 A)
Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Configure SODIMM settings for greenbayupoc. The SODIMM settings are
copied from mainboard/google/brya/variants/baseboard/brask/memory.c.
BUG=b:336955026, b:332230842
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS
using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM.
Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
1. MT62F1G32D4DR-031 WT:B (Mircon)
2. MT62F512M32D2DR-031 WT:B (Mircon)
3. H9JCNNNBK3MLYR-N6E (Hynix)
4. K3LKLKL0EM-MGCN (Samsung)
5. K3LKBKB0BM-MGCP (Samsung)
6. H9JCNNNCP3MLYR-N6E (Hynix)
BUG=b:337169542
TEST=build pass
Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.
BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.
Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Update the pad reset config for WLAN Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.
BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and
wakeup successfully using Wake on WLAN.
268 | 2024-05-07 13:56:44-0700 | S0ix Enter
269 | 2024-05-07 13:57:07-0700 | S0ix Exit
270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3
271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3
273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0
274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3
275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3
Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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According to Brox HW design, the PsysPmax is supposed to be 208W.
This patch changes PsysPmax setting from 21.5W to 208W.
Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903
Signed-off-by: Lawrence Chang <lawrence.chang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
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The smbus subsystem ID was inadvertently reversed when added in commit
6974bcd28e74 ("mb/google/parrot: override SMBus subsystem ID"), so
correct it.
TEST=build/boot Win10 on parrot, verify touchpad driver functional.
Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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The smbus subsystem ID was inadvertently reversed when added in commit
a6076cfcfdbe ("mb/google/butterfly: override SMBus subsystem ID"), so
correct it.
TEST=build/boot Win10 on butterfly, verify touchpad driver functional.
Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new Kingler follower 'Squirtle'.
BRANCH=corsola
BUG=b:333826091
TEST=emerge-corsola coreboot
Change-Id: I393738fc470ffc907f125647a46bf81c243708d7
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add data.vbt files for bujia supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.
changes:
1. "integrated DisplayPort with HDMI/DVI compatible"
-> "Integrated HDMI/DVI".
2. turn the AUX off.
BUG=b:327549688
TEST=build/boot various brya variants
Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81553
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brox uses PDC<->PMC direct connection for USBC mux configuration. Select
SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This
patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be
selected only when PDC<->PMC direct connection and CHROMEOS is not used.
BUG=b:332383540
TEST=USB3 plugged during G3, is detected after system boots from G3.
Cq-Depend: chromium:5484387
Cq-Depend: chrome-internal:7106592
Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
For Mithrax and Felwinter, port C1 is on the left side and port C2 is on
the right side. Correct the values accordingly.
The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports.
BUG=b:321051330
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT
Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
|
|
Within ec_acpi.c, USB-C ports are iterated to be matched with
corresponding mux. The iteration happens from 0 to the number of USB-C
ports. Given iteration index i, the port with PLD group_token of (i+1)
is matched with mux_conn[i].
Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2
to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token
of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus,
follow the convention to add conn1 to mux_conn[0] and conn2 to
mux_conn[1].
Otherwise, the kernel subsystem linking between Type C connector and USB
mux will be swapped.
BUG=b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT.
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
usbpd lines are workaround for devices without firmware patch to
connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875
Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
|
|
Configure eMMC DLL tuning values for Sundance board Samsung sku.
BUG=b:337741162
TEST=Use the value to boot on Sundance successfully.
Change-Id: I5f1e03c06c9f8567e757fed999730dff2551f1e0
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.
Change-Id: I49f5fda5628b2ebc76cd8db20c8f7fe85c676c7a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.
Change-Id: I38f46949d36359826317252e8d3434ad1b24382d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82156
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.
Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82155
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.
Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Fill GPIO table for pujjoga.
BUG=b:336469694
TEST=emerge-nissa coreboot
Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82044
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Update TDP PL1 value for the DTT optimization. The new value 18W is from
internal thermal/performance team.
- tdp_pl1_override: 15 -> 18 (W)
BUG=b:336684032
BRANCH=brya
TEST=built and verified MSR PL1 value.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
After this patch:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update I2C5 timing parameter values to meet I2C bus spec.
- fall_time_ns: 400 -> 200
BUG=None
BRANCH=brya
TEST=built and measure I2C5 timing parameters
Before:
tLOW : 1.88 us (spec >= 1.30)
tHIGH: 0.57 us (spec >= 0.60)
fSCL : 399.80 KHz
After:
tLOW : 1.60 us (spec >= 1.30)
tHIGH: 0.97 us (spec >= 0.60)
fSCL : 392.1 KHz
Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Create the riven variant of nissa reference board by copying the
template files to a new directory named for the variant.
The riven variant is a twinlake platform.
BUG=b:337169542
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RIVEN
Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iefe61d3ad51d355806716483248df5b1083b69bc
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82149
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add pujjoga supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068
3. Micron MT62F1G32D2DS-026 WT:B
BUG=b:337990338
TEST=Use part_id_gen to generate related settings
Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d
Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82135
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Based on schematic of 500E_GEN4S_ADL_N_MB_0418, generate overridetree.cb
settings for Pujjoga.
BUG=b:337611700
TEST=FW_NAME= pujjoga emerge-nissa coreboot chromeos-bootimage
Change-Id: I279f94044a22f25100a44b1abe2ef5fb6d0dd835
Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82109
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Adjust setting is from power team.
Change from 172W to 180W
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
check overrides setting
Change-Id: Icc8b12adc9fb9f680b05131c8d41212865223ca9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Adjust setting is from power team.
Itrip(GT) FVM 54
Itrip(SA) FVM 27
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
check overrides setting
Change-Id: I6d6cf7cecaac650a7b1784833b4afb8dffb3db2c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82176
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Correct .UserBd field to BOARD_TYPE_ULT_ULX from BOARD_TYPE_MOBILE. This
is from Intel's guidance for MRC to map the memory speed to proper POR
number.
BUG=b:332980211
BRANCH=brya
TEST=Built and compare the results of command 'dmidecode -t 17'
[Before]
(Same values in all of memory device handle)
Speed: 6400 MT/s
Configured Memory Speed: 6400 MT/s
[After]
(Same values in all of memory device handle)
Speed: 5200 MT/s
Configured Memory Speed: 5200 MT/s
Change-Id: Id16bcbc2d0cb4c2cf3008cf2ef1027ed98e93afb
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.
BUG=b:335124437
TEST=boot to OS from USB-A
boot to OS from SD Card
BRANCH=corsola
Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total
SPD size of 512 bytes. Set this as the default and remove the setting
from mainboard Kconfigs.
Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add GPP_F18 configuration in early_gpio_table.
Without this, DUT cannot get the proper state of this signal on early
phase. It allowed DUT to attempt to enter into dev mode when EC is in RW
currently, it causes the failure of autotest/firmware_DevMode.
BUG=b:337365524
TEST=built and run autotest firmware_DevMode
Change-Id: I2179bb10b431547bc35f332c74915a63495b779d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
|
|
GPP_D14 is floating when ISH is not being used and wasting power. Add
pulldown to prevent this from happening.
BUG=b:336654954
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
make sure OS boots up
HW team validated that power usage is 20 mW lower
Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.
BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup
using Trackpad.
246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3
247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3
248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67
249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3
250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3
251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67
Also suspend to S0ix and wakeup using Trackpad.
Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
The Fn key on Xol emits a scancode of 94 (0x5e).
BUG=b:327656989
TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Remove duplicate config entry CHROMEOS_WIFI_SAR as it is
used at the baseboard.
BUG=None
TEST=emerge-rex coreboot
Change-Id: Iabf0e490103c2097f3f033036839b77b5a0bb1b3
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81226
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.
BUG=b:333494257
TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage
Change-Id: Idb62e3f37e1480979ae529692455beb533434520
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82056
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module.
2.Describe the FW_CONFIG probe for the settings on glassway.
- WIFI_SAR_0 for Intel Wi-Fi module AX211
BUG=336051631
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81781
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Upload initial configuration for nova based on proto schematics.
Memory:
SAMSUNG 2G*4 K4U6E3S4AB-MGCL
HYNIX 2G*4 H9HCNNNBKMMLXR-NEE
BUG=b:328711879
TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage
Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
Add stop pin control for G2 touchscreen
BUG=b:335803573
TEST=build and verified Touchscreen work normally
Change-Id: I7e0bbc7722cdda6bcca0485009fcf8510b1f55e2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81971
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add STA_ER88577 MIPI panel for Wugtrio.
Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82055
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new GPIO port cbj-sleeve for kernel driver to call. At the same
time, a new rt5645 driver is added to replace the generic driver to
parse gpio. After entering the system, it is pulled high by the kernel
to enable the MIC function.
BUG=None
TEST=MIC function is normal
Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81774
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix custom_pld for USB2-C2 and USB3-C3 with same PLD group.
Update USB2-A4 PLD group token.
USB2/USB3 Type-C Port C2
"ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))"
USB2/USB3 Type-C Port C3
"ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST= emerge-ovis coreboot
Change-Id: Ieecf0f7dda671a421e4e4a4adbf83240fadd018d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Set unused pin to NC internal PU 20K
BUG=b:325674908
BRANCH=firmware-rex-15709.B
TEST= emerge-ovis coreboot
Change-Id: I78eddaa41c14721eeb6ff33a4cb15382853e430b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The DPTF parameters were defined by the thermal team.
Based on thermal table in 330817690#comment33.
Set 6w "tcc_offset" to "15" by fw_config.
BUG=b:330817690, b:290705146
BRUNCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I19100d960919dc3087fd067c24659de467eea276
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81997
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Commit 00b40090aecf ("mb/google/brox: Move hda verb to variant dir")
introduces a variant-specific file for the HDA verb tables, which
commit 1bf0c3f1897c ("mb/google/brox: Create lotso variant") was missing
which caused the build to fail when both patches were submitted. To fix
the tree, add this file to the newly created lotso variant.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a85115a204d9d9447a58da71eb65b1de963023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82014
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Create the lotso variant of the brox reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:333494257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_LOTSO
Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Others variant boards might use diff HDA Codec, so move hda verb
to brox variant dir.
BUG=b:314702466
BRANCH=None
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Device list:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ALC256
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek
Headphone detection:
evtest 8
Event: time 1713404716.656768, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1713404716.656768, -------------- SYN_REPORT ------------
Event: time 1713404722.802661, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0
Event: time 1713404722.802661, -------------- SYN_REPORT ------------
Change-Id: Id987c248c37dc8bdc63be7a2513fa8997b5ddc33
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81945
Reviewed-by: Poornima Tom <poornima.tom@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.
BUG=b:333325006
TEST=emerge-brox coreboot depthcharge with no errors
Change-Id: I0e220787d6ac73ec8fa2469ed958981d0801920e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Support Memory for Hynix H58G66AK6BX070 and Samsung
K3KL9L90CM-MGCT in mem_parts_used list, and generate SPD ID for these
parts.
DRAM Part Name ID to assign
H58G66AK6BX070 4 (0100)
K3KL9L90CM-MGCT 5 (0101)
BUG=b:335341310
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: Ic07ec36a8015ce6433196a93e894b818a515b954
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81955
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
|
|
Enable SaGv support for brox
BUG=None
BRANCH=None
TEST=Boot brox with SAGv enabled and verify in fsp debug logs
Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Several brya-based boards use UFS for storage, so enable the edk2 UFS
driver when using the edk2 payload.
TEST=build/boot google/brya (banshee, craaskov), verify internal boot
media functional with edk2 payload.
Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Several zork-based boards use eMMC for storage, so enable the edk2 eMMC
driver when using the edk2 payload.
TEST=build/boot google/zork (morphius, vilboz), verify internal boot
media (both eMMC and NVMe) functional with edk2 payload.
Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add a new Krabby follower device 'Veluza'.
BUG=b:333630131
BRANCH=corsola
TEST=none
Change-Id: Idedcbfbddd6d98a51cf28a0963d68f6d8c68382c
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81791
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
1. Remove non-use i2c address 0x10, 0x24 and 0x40 of touch IC for touch screen
2. Add new i2c address 0x5d of Goodix touch IC for touch screen
3. Add new i2c address 0x38 of Focal touch IC for touch pad
BUG=b:333804572
TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage
Change-Id: I8e2c60820a07b99b69860fd4f6557b448aef2341
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Create the pujjoga variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:333839287
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOGA
Change-Id: Ia8eb11eb65f9013e83abd45eefe7705d05b8697e
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81891
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.
TEST=build/boot zork (morphius) with SMMSTORE enabled.
Change-Id: Ifd3be9b0757e270d2f106e2fbebf3991e49dec65
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.
TEST=build/boot skyrim (frostflow) with SMMSTORE enabled.
Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.
Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81867
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.
TEST=build/boot guybrush (dewatt) with SMMSTORE enabled.
Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The karma variant, being a Chromebase, has an internal eDP output for
the built-in display whereas the fizz/endeavour variants do not. Use
separate gma-mainboard.ads files so that karma's internal panel works
properly with libgfxinit.
TEST=build google/fizz (fizz/karma) with libgfxinit enabled, ensure
correct gma-mainboard.ads file is included in the build.
Change-Id: Ia6aca538ba8c13b48aa80901222071d704b5f0c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Create the greenbayupoc variant of the brox reference board by copying
the template files to a new directory named for the variant.
BUG=b:329530883
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_GREENBAYUPOC.
Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Add a new Krabby follower device 'Skitty'.
BUG=b:331702790
TEST=emerge-corsola coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: I2f12bccfda591a5baf8d23d217b6f1f81b059d15
Signed-off-by: Herbert Wu <herbert1_wu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81772
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Geoffrey Chien <geoffrey_chien@pegatron.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
|
|
Recent changes to the ITE 8772F SIO code caused the initial fan PWM
to change from 0 to 50%; set it to 30% to reduce fan noise while
still providing some temp control before the OS/ACPI takes over.
TEST=build/boot google/beltino to payload, verify fan noise is
negligible.
Change-Id: I0177235d73e051f02b5333cf1d735556382b919f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81513
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.
The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.
Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also
initializing it (if ISH is enabled) to be NF2 (ISH_GP4). Also took
the liberty of alphabetizing all the ISH GPIOs to they're easier to
search through.
BUG=b:316421831
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
Make sure that brox device still boots up with this change.
Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81789
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fill GPIO table for Sundance.
BUG=b:327520553
TEST=emerge-nissa coreboot
Change-Id: I53ed5874347006985ca5231d1531fa519088f796
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81613
Tested-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: I66265727b68b6ad10722439314b466298dbfff28
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In next phase, craaskov will remove external fivr. Use the board
version to config external fivr for backward compatibility and
show message.
BUG=b:330253778
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:333605309
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared.
Change-Id: I6e2230715d783ea7108d71699fd19684ce19e2ff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds a new variant trulo for the baseboard trulo.
BUG=b:333314089
TEST=abuild -a -x -p none -t google/brya
Change-Id: I91157d252ef56c8938bfc08ed0f734c5dc7e614d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81627
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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