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1) Add all required changes for eSOL support.
2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo.
The CSOT (MNC207QS1-1) panel is used for the devicetree.
BUG=b:362895813
TEST=On-screen text message seen during MRC training on Trulo SKU1.
MRC: no data in 'RW_MRC_CACHE'
bootmode is set to: 0
DP PHY mode status not complete
DP PHY mode status not complete
DP PHY mode status not complete
...
Informing user on-display of memory training
Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
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Update verb table provided by Realtek on 20240710.
Restults: SNR > 90 (spec>=90).
BUG=b:349996984
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: Ic4f03d09010efa7e32713b2697d5832255f64317
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83920
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We have to reset the USB hub as early as possible. Otherwise the USB3
hub may not be usable in the payload. This design has been introduced
since Cherry.
TEST=build pass.
BUG=b:317009620
Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84024
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add usb host function support.
TEST=read usb data successfully.
BUG=b:317009620
Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com>
Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL).
BUG=b:358439747
TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C.
Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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With `probe unprovisioned` fw_config rule, there is no need to define an
explicit STORAGE_UNKNOWN option. Hence remove it.
BUG=None
TEST=Build Lotso FW image.
Change-Id: Ia170a6e006cb51e95fbaf3efe1106ca907165eca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84094
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This feature is not required in Brox devices. Hence disable the
concerned device.
BUG=None
TEST=Build Brox firmware and boot to OS. Ensure that the concerned
device is disabled in the OS.
Change-Id: I355852c780c552e6f9b2c28508f53580f392c1b9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84093
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
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Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login
screen, it is because it inserts 12 blank frames if it receives the
unmute in VB-ID.
Always override the mute in VB-ID to avoid Tcon EC detected the
audiomute_flag change.
BUG:b=357764688
BRANCH=firmware-nissa-15217.B
TEST:Verfied on Anraggar and cannot reproduce the issue
Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
TEST=Build and boot nivviks. Monitor the camera LED blinking
during boot.
Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
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This patch removes the HAVE_ACPI_RESUME config option from the Google
Rex mainboard configuration. The Intel Meteor Lake SoC does not support
S3 (ACPI sleep state) entry/exit, and attempting S3 validation could
lead to abnormal platform behavior. This change ensures that `_S3` is
not listed as a valid wake source in the DSDT (Differentiated System
Description Table) after booting to the OS.
BUG=b:351025543
TEST=Booted google/rex successfully and verified that the `_S3` name
variable is not present in the DSDT.
Change-Id: I730ade628eea84c60ba003a0c871e729b0ee0a9f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84081
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Introduce a sandybridge-style devicetree setting for SPD addresses,
and use it instead of runtime code in mb_get_spd_map() for all
haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all
boards except google/slippy.
Patch also covers recently added Z97 boards using Broadwell MRC.
Also update util/autoport to match.
abuild passes for all affected boards.
autoport builds, but otherwise untested.
Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit aa6865291a7ddfae4c67fcfc55ebd0c13a376807.
Reason for revert: We applied this patch for touchpad stuttering issue
for XOl, but the same touchpad problem was reported. So we would revert
this change and apply kernel patch (crrev/c/5808335) to avoid the
touchpad issue.
Change-Id: I78139932e76dbd4128fb325dd70b7dcff3bcc81c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Initialize SPI NOR Flash Controller (SNFC) in the bootblock.
TEST=read nor flash data successfully.
BUG=b:317009620
Change-Id: I88960ce7a50f67ea6f402884b714cb205836a6d8
Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83924
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the weak function. Combine all the getting descriptors together.
BUG=b:279144932
TEST=Build
Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83646
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG
for WIFI_CATEGORY to choose the right wifi_sar hex file.
Below is the file mapping:
wifi_sar_0.hex = wifi6
wifi_sar_1.hex = wifi7
BUG=b:345596420
TEST=emerge-nissa coreboot chromeos-bootimage
Cq-Depend: chrome-internal:7607427
Change-Id: If8339a2a1d32d3e885ef87ea2ec2847f107f1fbd
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84051
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify DPTF parameters from thermal team.
1. Add TCHG.
2. Modify the charging limit.
BUG=b:360066326
TEST=Modify Thermal according to design requirements
Change-Id: Ia7050b552656a70da0c992e4f54b02ccb6a7c114
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83929
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar
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Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:348258637
TEST=Local build successfully and boot to OS normally.
Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table.
BUG=b:358472598
TEST=Build and verified test result by EE team
Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83904
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: I0908ff500434401bf89a5313427cf304f32cf929
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add the condition of unprovisioned fw_config to enable all storages
and devices. It's for first boot on all storags and preliminary test
in factory when fw_config is unprovisioned.
BUG=None
TEST=Build jubilant firmware and boot to OS on storages when fw_config
is unprovisioned and ensure all devices are enable.
Change-Id: Ia14632744c34548e2c201dfc58d82515cdd02df0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84002
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Storage devices are very critical to boot to OS. When probe list is
defined for storage devices, all of them get disabled when fw_config is
unprovisioned - a typical situation in the factory. Fix this by
configuring the storage devices in device/override tree to probe and
enable them when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83984
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the voltage value measured by the USB2 pin of the wlan is 500mv,
it does not meet the design requirements. Adjusting the port length
can reduce the voltage to 450mv, which meets the expected settings.
BUG=b:361037189
TEST=1. The voltage measurements are as expected.
2. The Bluetooth and WiFi functions of the wlan module are
verified to be normal.
Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Enables early serial console for debugging.
TEST=build/boot drobit, verify console output available starting in
bootblock on CPU UART (/dev/ttyUSB1) vs ramstage.
Change-Id: If94eb8caca3469143433fef06b972050f886be6a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Enable Intel CrashLog diagnostic feature by default on all Google
Dedede variants.
BUG=b:354834461
TEST=Built for Google Dedede and verifed that CrashLog is enabled by
default.
Change-Id: Ib0487bd6a5bfdad2a80fd0787e009e48f4527d38
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Kinox has two VBT options, selected via fw_config. Add the second
option to CBFS, and update the original file.
Extracted from Google_Kinox.14505.704.0.bin.
TEST=build/boot kinix, verify firmware display init successful and
payload menu visible. Verify correct VBT selected via cbmem log.
Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83996
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify brox DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I5cd36640677996209beb8fe29f522ff8e07ebf00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify rex DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I3fdc02a82d197fd2b075e0a66c578149cef3a69f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=firmware-brya-14505.B
TEST=verify brask, nissa, or brya DUT is able to power down and stay
powered down when selecting the "Power off" button in the firmware dev
screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Adjust settings as recommended by thermal team.
Set tcc_offset value to 12 in devicetree.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I0ae97bb0b2dbb2fe8f35221522506ec1f7da47f6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83971
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: I87cfbdd0b8a97d84a96af373855219c60f39f173
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: Ib654f22033c68edbc602f14537aaa2151800598d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83943
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change STORAGE_UNPROVISIONED to STORAGE_UNKNOWN depend on depthcharge setting.
BUG=None
TEST=emerge-brox coreboot
Set STORAGE_UNKNOWN on jubilant, check that NVMe and UFS can boot.
Change-Id: I4cfd7322c2940862dfbae46e85522715cd7534c1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83935
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
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Before:
I2C2 - 431KHz
I2C4 - 413KHz
After:
I2C2 - 364KHz
I2C4 - 370KHz
BUG=b:351968527
TEST=Rate of the actual measured machine is pass.
Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83906
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Set up soundbar-related GPIOs for updating.
BUG=b:358435383
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I517da8de90487533e49e46649c5acf4ccfcc5160
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes WWAN configuration from the bootblock.
It appears that setting it up in the bootblock may not be necessary.
Configure in bootblock,the seq will be triggered at the same time.
The customer would like us to leave some buffer for EN to RST.
BUG=b:357764679
TEST=Build and verified test result by EE team
Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83792
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls `xhci_host_reset()` function to perform XHCI
controller reset.
Currently, the PMC IPC times out while sending the USB-C (0xA7) command
during poweron from S5 (S5->S4->S3->S0).
On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:
localhost ~ # cbmem -c | grep ERROR
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:0 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:1 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x20a0 failed
This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).
During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.
This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.
Supporting Doc=Intel expected to release a TA (Technical Advisory)
document to acknowledge this observation and supported W/A for ADL
generation platforms.
Till that time, keeping this W/A as part of the google/brya specific
mainboard alone.
Note: other ADL-SoC based mainboards might need to apply the similar
W/A.
BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.
Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR
No PMC timeout error is observed with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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1.Set unused device's GPIOs to NC based on fw_config.
2.Disable config for nvme, ufs and CNVi based on fw_config.
3.Add fw_config STORAGE_UNKNOWN to enable all storages
for the first boot in factory.
BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge
check fw_config messages in ap log
verify devices on/off by fw_config on jubilant
Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Locking GPP_F15 causes DUTs with fingerprint sensor to not be able to
correctly power down and stay powered down. This pin does not need to
be locked.
BUG=b:359692570, b:356750516
BRANCH=firmware-brya-14505.B
TEST=`FW_NAME=gimble emerge-brya coreboot chromeos-bootimage`, flash and
boot gimble into developer mode, then reboot into dev screen and select
the "Power off" button and verify gimble powers off and does not power
itself back up.
Change-Id: I1c73035b02021b0d1268cd46dcd0841621556ad5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The AP console log contains "HECI: No CSE device" and the system cannot be entered.
BUG=b:359474142
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
The "HECI: No CSE device" message for AP log disappered
Change-Id: I488056dc8bca2174dd96c28793e3202b7aae890c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83905
Reviewed-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Extracted from coreboot-Google_Phaser.11297.296.0.bin.
Fixes display init on newer LASER14 boards.
TEST=build/boot google/phaser, observe display init successful.
Change-Id: Icb48edb4e74f147e3458f845d921a15a2d1906da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83897
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In next phase, riven will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message.
BUG=b:359062365
TEST=build, boot to OS, suspend/resume work normally.
Change-Id: Id5f538b2eda7820a922b8d9ee14b2bae7df3726c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Brox does not have PCIe WWAN or discrete GPU. Hence no need to power
them off during suspend. Hence also remove the MPTS ACPI method.
BUG=None
TEST=Build Brox firmware and boot to OS.
Change-Id: Ia239c3f038ce31934efb0a391350fa0f786e3fcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83788
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brox uses Ti50 which always supports long interrupt pulse. Hence no need
to override GPIO PM.
BUG=None
TEST=Build Brox firmware and boot to OS. Perform suspend/resume for 25
cycles.
Change-Id: I6a138c1953714bc29570db587594cab8f315a4ec
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83856
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables the TCSS XHCI in the devicetree to solve the genesys
hub enumeration issue.
BUG=b:348332200
TEST=Able to build google/nova and ensure lsusb can list genesys
hub device.
Change-Id: Ic8e25756a2975e884434c4c7e3d587f4c1f0ed0b
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83845
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Confirm with EE, the GPP_C1 don't need PU 20K.
So modify GPP_C1 setting to remove PU 20k
Schematic version: 500E_GEN4S_ADL_N_MB_0418
BUG=b:358162951
TEST=Build and boot on pujjoga.
Change-Id: I7ad16cd29ab467d3eac74dab40522c577d91c747
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83818
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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1. The P sensor need follow WWAN FW_CONFIG to enable/disable
2. Modify GPP_H19 setting to PAD_CFG_GPI_APIC to fix PLT test fail
Schematic version: 500E_GEN4S_ADL_N_MB_0418
BUG=b:357998089
TEST=1. Boot to OS and verify the P sensor devices is set based on
fw_config.
2. Confirm that the PLT test can pass successfully.
Change-Id: Ic3610180c8cf99eba9367e26bfc3666410af19f7
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:348125053 b:348126380
TEST=emerge-nissa coreboot
boot with elan TS, make sure elan TS is functional.
Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83876
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change-Id: I27568d1205216f697b48ffb09ce5208505718978
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83863
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update dptf settings for EVT.
BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge
Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update touchpad settings.
BUG=b:342867386
TEST=ensure touchpad is working.
Change-Id: Ibf62470b7fd921065201894a63d7e2a83dad53ce
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Add TPM TIS ACPI interrupt configuration, set teliks's
`TPM_TIS_ACPI_INTERRUPT` to 13.
BUG=b:352263941
TEST=emerge-nissa coreboot
Change-Id: Iaed51e0bb8abac0ed0b35bfcf12e95fd34f92242
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83832
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.
BUG=b:352263941
TEST=DP function of MB and DB workable
Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables pch_hda_sdi_enable for the trulo baseboard and
removes SDI lanes update from its variants.
BUG=b:350931954
TEST=Boot verified on google/craask and google/tivviks
Change-Id: I2e0f43b8fffb5e583089769d2c7446b476ce5d5d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345373187
TEST=Build and test on google/rex0, check BRDS is shown in SSDT.
Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72
Change-Id: I82f6290cb1934e2c0597286702f93e3789e8f345
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345373187
TEST=Build and test on karis, check BRDS is shown in SSDT.
Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83791
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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This reverts commit 1f1d8d2bcae64baea19d0e947ba5572a45f46eec.
Reason for revert: Intel® Wi-Fi 6E AX211 (CNVi) does not need Bluetooth
Regulator Domain Settings and therefore, the bluetooth companion
device declaration for CNVi is unnecessary.
BUG=b:345373187
TEST=Able to build and boot google/karis.
Change-Id: I296ddb93659af144e1a82a6b8219c9811c5fe545
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83843
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iab7e9f3d17c87576761333c4b62c40eea5e424a5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The Fn key on jubilant emits a scancode of 94 (0x5e).
BUG=b:324079605
TEST=Flash jubilant, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I963b0aa85598097fea69ec34d1e79ec0bbec3db3
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83821
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refactor mainboards' code to use the new GPIO driver.
TEST=Put Google Jecht to S3 sleep and check if the LED blinks.
Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add SAR Sensor SX9324 for WWAN:
- Apply DRIVERS_I2C_SX9324
- Config GPP_H19 for IRQ
- Add SX9324 registers settings based on tuning value from SEMTECH.
Refer to datasheet:
https://chromeos.google.com/partner/dlm/avl/component/3624/
BUG=b:345327104
TEST=Build and verify on jubilant
Change-Id: I629117f20ca513dc0c8eaa91744ad33e162ba4bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83779
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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wifi.SetTXPower test fail, so enable wifi sar.
BUG=b:351698478
TEST=emerge-brox coreboot
Change-Id: Ibf5425e72eddc45e376ef4e2d077180dab502200
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:350844195
TEST=emerge-nissa coreboot
boot with G2 TS, make sure G2 TS is functional.
Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83823
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MKBP device is required for passing events from input sources to AP.
Input sources include buttons (power, volume); switches (lid, tablet
mode) and sysrq.
BUG=b:357521411
TEST=Build coreboot and switch tablet mode on orisa.
Change-Id: Ic712f53fb4063347c38df05167f0100afc06f979
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83819
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.
* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
* `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
* `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.
BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.
Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Add the support LP5 RAM parts for fatcat:
DRAM Part Name ID to assign
H58G56BK7BX068 0 (0000)
BUG=b:347669091
TEST=emerge-fatcat coreboot
Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
|
|
This change enables storing the ISH firmware version on the Trulo
baseboard by selecting the `SOC_INTEL_STORE_ISH_FW_VERSION` config
option.
BUG=b:354607924
TEST=Able to dump ISH version on trulo.
> cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.7780
Change-Id: I69a7fa19c53f435ef1f6306b259f703c7b196137
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83820
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
The Fn key on awasuki emits a scancode of 94 (0x5e).
BUG=b:355538142
TEST=Flash awasuki, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Ic7aa183bf314fed4901133dc70d848d84fab0784
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
1. Change driver form i2c/hid to i2c/generic.
2. Add fw_config for touchscreen.
BUG=b:351968527
TEST=ectool cbi set 6 0x0x10200a0;
touchscreen functions normally;
Change-Id: Ifd6330be8924d4873f0efab3ce404168a62099eb
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83704
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch configures the GPIO pins to enable ISH on the Trulo device,
in accordance with schematic_20240607.
BUG=b:354607924
TEST=Builds successfully for google/trulo.
Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83781
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch configures the GPIO pins to enable ISH on the Orisa device,
in accordance with schematic_20240607.
BUG=b:354607924
TEST=Builds successfully for google/orisa.
Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83656
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
|
|
Adjust Touchpad I2C fall time configuration such that it meets the
I2C fast mode specification(<= 400KHz).
BUG=b:328670295
TEST=Build Brox firmware and boot to OS. Confirm the I2C bus
frequency(375 KHz), rise(650 ns) and fall(330 ns) times meet the
specification.
Change-Id: I0006bfb9bb5839ffa1248d9f2ea055160ed0936e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83755
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
Update GPIOs for WWAN and USB Camera functions.
BUG=b:341188351
TEST=Build and verify on jubilant
Change-Id: I145aa994767ddc59be519b96017af71badf82734
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
|
|
Define ISH main firmware name so ISH shim loader can load firmware
from file system.
BUG=b:354607924
TEST=Boot trulo board, check that ISH is enabled and loaded
lspci shows: 00:12.0 Serial controller: Intel Corporation Device 54fc
Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83671
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Because Awasuki doesn't have SD card, disable related configurations.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: I1b0d2a9c2f9cdd4bca7c30cdc454ffa84b293146
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83706
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
BRANCH=None
BUG=b:348171026
TEST=Test on TI PDC device
Cq-Depend: chromium:5691079
Cq-Depend: chromium:5691080
Cq-Depend: chrome-internal:7464767
Original-Change-Id: I6ffb8bdb2245a74b0d5270435d0ffc8a44e7c2a6
Original-Signed-off-by: Bob Moragues <moragues@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5691110
Original-Reviewed-by: YH Lin <yueherngl@chromium.org>
Change-Id: Iac5b4cd4dcb1d274553f78e9d4295f8f9ad8a863
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This patch introduces the following changes,
- Remove TCSS XHCI (USB 3.x) devicetree settings
- Update Over Current (OC) & USB 2.0 config
- Update TCSS-XHCI capabilities
BUG=b:348332200
TEST=Able to build google/nova and ensure lsusb can list genesys
hub device.
Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83707
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch removes the PMC MUX related setting from devicetree as Nova
doesn't include a MUX for it's USB-C port.
BUG=b:348332200
TEST=Able to build google/nova
Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.
BUG=none
TEST=Able to build and boot google/rex0. Able to see all debug prints
over CPU uart.
Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The previous uploaded verb table is not fully applied due to
configuration error. Uploaded the verb table provided by Realtek which
can be found in b:336967284.
BUG=b:326412504, b:336967284
TEST=deploy and check volume
Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Terry Cheong <htcheong@chromium.org>
|
|
DC offset of class-D amplifier is 7mV in Brox which is larger than the expected 3mV.
Add a section in the verb table to enable class-D calibration based
on the updated verb table provided by Realtek in b:342506575 comment#6.
This improves the offset to be less than 1mV.
BUG=b:342506575
BRANCH=main
TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \
playing -100dB sine waves.
Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Create the jubilant variant of the brox reference board by copying
the template files to a new directory named for the variant.
BUG=b:348543712
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUBILANT.
Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
|
|
Create the teliks variant of the nissa reference board by copying
the anraggar files to a new directory named for the variant.
BUG=b:352263941
BRANCH=None
TEST=1. util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TELIKS
2. Run part_id_gen tool without any errors
Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch drops fw_config probing for ISH because ISH IP should
remains on by default for all Trulo variants.
Additionally, removed the redundant ISH entries from variant
override devicetree.
BUG=b:354607924
TEST=Able to verify ISH PCI Device is available while booting eMMC sku.
```
lspci
00:00.0 Host bridge: Intel Corporation Device 461c
...
00:12.0 Serial controller: Intel Corporation Device 54fc
...
00:1a.0 SD Host controller: Intel Corporation Device 54c4
```
Also, able to enter S0ix with this patch.
```
> suspend_stress_test -c 1 --ignore_s0ix_substates
At AP console:
s0ix errors: 0
s0ix substate errors: 0
s0ix pc10 errors: 0
At EC console:
power state 5 = S0ix, in 0x38d87
```
Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum
time (98ms) from 2sec.
BUG=b:349595391
BRANCH=firmware-brya-14505.B
Test=Verified on xol
Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Streamline variant-level overrides by removing redundant entries that
already exist in either the SoC-level or the platform-level configurations.
BUG=None
TEST=emerge-nissa coreboot
Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This change adds a new USB2 Bluetooth device configuration on Port 10
for the Trulo variant.
* A new `drivers/usb/acpi` chip is added with:
* `desc` set to "USB2 Bluetooth"
* `type` set to "UPC_TYPE_INTERNAL"
* `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
* `device` referencing `usb2_port10`
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This change removes the configuration for the unused USB2 Port 6
(index 5) and its associated Bluetooth device on the Trulo variant.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83665
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rishika Raj <rishikaraj@google.com>
|
|
This change removes the configuration for the unused USB2 Port 6
(index 5) and its associated Bluetooth device on the Orisa variant.
It also cleans up a redundant newline before the `serial_io_i2c_mode`
definition.
BUG=b:351976770
TEST=Builds successfully for google/orisa.
Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83664
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rishika Raj <rishikaraj@google.com>
|
|
This patch moves the configuration for integrated Bluetooth
functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard.
This change is necessary to support the CNVi BT module on Trulo
variants. The configuration is skipped for Orisa.
Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to
support the CNVi BT module.
Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for
CNVi WLAN has been removed.
This change ensures proper Bluetooth connectivity is applicable for all
Trulo variants including Orisa and Trulo.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices.
2. Update fw_config probe to enable/disable devices in devicetree.
3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config
is enabled.
BUG=None
TEST=emerge-nissa coreboot
Change-Id: Id3a22aa2206e86fdca6f6fadbc849572890fee58
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83657
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Orisa variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
BUG=b:345112878
TEST=Able to enter S0ix on Orisa eMMC sku after disabling UFS
during boot path.
Change-Id: I969b0c0c785ed4c408f6fc6de71e7d0c1a1ea27c
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Trulo variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).
BUG=b:355384185
TEST=Able to enter S0ix on Trulo eMMC sku after disabling UFS
during boot path.
Able to grep below debug prints while booting the eMMC sku.
[INFO ] FW_CONFIG value from CBI is 0x20000000
[INFO ] Disabling UFS controllers
...
[INFO ] fw_config match found: STORAGE=STORAGE_EMMC
Change-Id: I06a84fa8c3843edae5932e19d394b18b72ace422
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83654
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
|
|
In preparation for dropping the Chrome-EC submodule, remove the ability
for Chrome-EC and PD components to be built as part of coreboot.
These components have not been used or buildable for many years.
Change-Id: Ibf6bd43e755cf5b4d2aa8a42f38dc52e7023e9b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83638
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
The Fn key on riven emits a scancode of 94 (0x5e).
BUG=b:345231373
TEST=Flash riven, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Iddedd08fc50e8e8e369ce3d73edf0f3077867e87
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch configures GPIO pins as required for booting the Trulo
device from ramstage.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I7b540416083a923ba4d2e52aa8edafb4bfb9ac0e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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