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authorMatt DeVillier <matt.devillier@gmail.com>2024-08-19 16:16:34 -0500
committerFelix Held <felix-coreboot@felixheld.de>2024-08-22 13:25:55 +0000
commit7909b88789027a54a9f62bd738fe6e49093c068b (patch)
tree5650cd2725a6111926fdeab46ea165872f4b4c5a /src/mainboard/google
parent1c6548d5ccfcc550b209ac9cef401883ffdc34ff (diff)
mb/google/volteer/var/drobit: Set UART GPIOs in bootblock
Enables early serial console for debugging. TEST=build/boot drobit, verify console output available starting in bootblock on CPU UART (/dev/ttyUSB1) vs ramstage. Change-Id: If94eb8caca3469143433fef06b972050f886be6a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/volteer/variants/drobit/gpio.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/drobit/gpio.c b/src/mainboard/google/volteer/variants/drobit/gpio.c
index f7ee4eefbf..f36b89c420 100644
--- a/src/mainboard/google/volteer/variants/drobit/gpio.c
+++ b/src/mainboard/google/volteer/variants/drobit/gpio.c
@@ -135,6 +135,11 @@ static const struct pad_config override_gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+ /* C8 : UART0 RX */
+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+ /* C9 : UART0 TX */
+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */