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path: root/src/mainboard/google
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2023-02-18mb/google/geralt: Report SKU ID and panel ID for unprovisioned devicesYidi Lin
To make MIPI/eDP panel functional on unprovisioned devices, it requires passing SKU ID and panel ID info to the payload(depthcharge) to load the corresponded device tree for kernel. BUG=b:247415660 TEST=cbmem -1 |grep "SKU Code". Change-Id: Id2254729b7bd621d1e9bc520e8f40916d0f81030 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73076 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-17mb/google/skyrim/var/frostflow: Update Elan touchscreen power sequenceFrank Wu
Based on product spec v1.4, update T3 timing to 150 ms from 300 ms BRANCH=none BUG=b:269041202 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-02-17tree: Use __func__ instead of hard-coded namesElyes Haouas
Change-Id: I87e383ce2f28340dbc3c843dbf2ed0e47c00a723 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_AEI: ACPI Event Interrupts"Elyes Haouas
Change-Id: I58a4e4fbd1a43462147daa58a5fda767cfd59c06 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ADR: Address" commentElyes Haouas
Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17mb/google/dedede/var/dibbi: Update devicetree for enabling audioSam McNally
Enable HDA device and update jack codec HID from ALC5682I-VD to ALC5682I-VS. BUG=b:268309238 TEST=kernel detects audio DSP and rt5682s BRANCH=dedede Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-17mb/google/nissa/yaviks: Tuning eMMC DLL value for eMMC initialization errorchia-ling.hou
BUG=b:265611305 TEST=Reboot test 2500 times pass Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-02-16mb/google/brya: Add new baseboard hades with variants hadesEric Lai
Add a new baseboard for hades, an Intel RPL based reference design. Also, add variants for the reference boards hades. This commit is a stub which only adds the minimum code needed for a successful build. Need update gpio and memory DQ pins after final shchematic comes out. BUG=b:269371363 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-16mb/google/geralt: Pass XHCI_INIT_DONE to the payloadYidi Lin
BUG=b:269059211 BRANCH=none TEST=emerge-gralt coreboot Change-Id: Ia2ec6db332939f1ac629cda9a0784a12c92d91da Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73056 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-02-16mb/google/rex: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Mainboard variants to override the USB ports as per the target board design. TEST=Able to build and boot google/rex with all USB ports are working as expected. Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-16mb/google/brask/var/aurash: Initiate coreboot settingZoey Wu
Initial Aurash configuration base on moli design. 1. Set up gpio. 2. Add memory config. 3. There is no SD card setting on aurash, remove it from overridetree. 4. Follow moli psys schematic design. 5. Enable BT offload. BUG=b:269063331 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: Ia9088cc2937bab72c8c22af592392384a10616a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-02-15mb/google/brya/var/omnigul: Add memory parts supportJamie Chen
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) Samsung K3KL8L80CM-MGCT 2) Hynix H58G56BK7BX068 3) Micron MT62F1G32D2DS-026 WT:B 4) Micron MT62F512M32D2DR-031 WT:B 5) Hynix H58G56BK8BX068 BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com>
2023-02-15mb/google/brask/var/constitution: update gpio settingsMorris Hsu
Configure GPIOs according to schematics TEST=emerge-brask coreboot Change-Id: Ib27f1c334cad47b3be57f57b7cc8ca5530118328 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72945 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-15mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHzTarun Tuli
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements. For SCL, the t-high time is now over the min 600ns requirement for 400KHz operation (measure at over 700ns). Also, this change does not violate other parameters - rise time, setup time and hold time. BUG=b:264704732 TEST=Verified all timings meet spec now Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15mb/google/brya/acpi: Update checksum in NVPCF DSM subfunctionTarun Tuli
The NVPCF DSM subfunction specified a incorrect checksum. Update this function to the proper checksum of 0xaf. BUG=b:214581372 TEST=build Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15Revert "mb/google/brya/vell: Add PS1/PS2 cutoff point"Shon Wang
This reverts commit e30695dbe196ea42864ad03af799706eaae11f02. for meet thermal criteria, modify PS1/PS2 cutoff to default value BUG=b:229803757 BRANCH=brya TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72833 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-15mb/google/brya: Add Kconfig for TPM I2C busZoey Wu
Add TPM I2C for aurash to avoid TPM I2C fail. BUG=b:269050049 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: I1947d2e1189f46d8dab01837f75de7cb6e9e0579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14mb/google/skyrim: Create whiterun variantIsaac Lee
Create the whiterun variant of the skyrim reference board by copying the winterhold files to a new directory named for the variant. BUG=b:265955979 BRANCH=None TEST=emerge-skyrim coreboot and boot up on Whiterun Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7 Signed-off-by: Isaac Lee <isaaclee@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-14mb/google/skyrim: Add support for and select USE_SELECTIVE_GOP_INITMatt DeVillier
Add a FMAP region to support caching GOP-driver-modified VBIOS tables. Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP. Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP. BUG=b:255812886 TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS in CBFS, cached VBIOS data is used when not booting in recovery or developer modes. Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-14mb/google/hatch: drop include for puff baseboardMatt DeVillier
Commit 45b1da33c80a ("mb/google/hatch: split up hatch and puff baseboards") moved puff out from under hatch into its own mainboard dir, but this basebaord include was left behind. Delete it as it's not needed. TEST=build hatch variants Change-Id: I9045c52006fd232552541d68972d831c8b52da27 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14mb/google/rex: Set `SkipExtGfxScan` FSP-M UPDSubrata Banik
This patch overrides `SkipExtGfxScan` UPD as the Rex device is equipped with an on-board graphics device hence, skip scanning external GFX devices. BUG=b:228002764 TEST=Able to save ~1ms+ boot time on google/rex. FSP FPDT Data is showing the timestamp between those function calls. Without this patch: [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22 [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131 With this patch: `CheckOffboardPcieVga` is not getting called. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-13mb/google/skyrim/var/frostflow: Update Package Power ParametersJohn Su
Follow thermal table to modify setting. "stapm_time_constant_s" = "200" to "275" BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7fe05fe1c17258a3323b8d04302212e76a388797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-13mb/google/brya/var/lisbon: Update gpio tableRobert Chen
eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH. BUG=b:263548436 TEST=emerge-brask coreboot Change-Id: Iffbc9dc932325cdd2176b36795a2ff1b3690fbf8 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72941 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-13mb/google/brya/var/gladios: Update gpio tableRobert Chen
eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH. BUG=b:263548436 TEST=emerge-brask coreboot Change-Id: I610d53059e86945693bc5b3d7e43462e53640564 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72940 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-11soc/amd/*: Add SOC_NAME in fw.cfg(s)Zheng Bao
2/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: I18f73462a3995038fe93750320dfc053fec969ba Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-10mb/google/brya/var/brya0: add RPL 28W dptf settingsSumeet Pawnikar
Add Raptor Lake (RPL) 28W dptf settings for Brya0 BUG=b:235311241 BRANCH=firmware-brya-14505.B TEST=Built and tested on brya Change-Id: I5d06c1ace5b481012ea39f2a57570eb6330479cb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/skolas: add RPL 28W dptf settingsSumeet Pawnikar
Add Raptor Lake (RPL) 28W dptf settings for Skolas BUG=b:235311241 BRANCH=firmware-brya-14505.B TEST=Built and tested on skolas Change-Id: I4364ca6a50906c2a6dd0e754238264c680e7ebd0 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-10mb/google/brya/var/brya0: update PL1 minimum valueSumeet Pawnikar
Update Power Limit1 (PL1) minimum value to 15W based on the Brya design. BRANCH=firmware-brya-14505.B BUG=b:235311241 TEST=Built and tested on Brya system Change-Id: Ifd5256221b82eae2cfe8009918f8ff4791751b4d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72868 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/skolas: update PL1 minimum valueSumeet Pawnikar
Update Power Limit1 (PL1) minimum value to 15W based on the skolas design. BRANCH=firmware-brya-14505.B BUG=b:235311241 TEST=Built and tested on Skolas system Change-Id: I1027ca2bf2323ac959474ee6c38e47fa530113da Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72727 Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/brya0: update dptf thermal settingsSumeet Pawnikar
Update dptf thermal settings as per suggested by thermal team. Control fan based on TSR sensors, not based on CPU sensor temperature which changes too fast. BRANCH=firmware-brya-14505.B BUG=b:235311241, b:261749371 TEST=Built and tested on Brya system Change-Id: I58bc7132086b0776ee191a242bd1302554f3854f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72867 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/skolas: update dptf thermal settingsSumeet Pawnikar
Update dptf thermal settings as per suggested by thermal team. Control fan based on TSR sensors, not based on CPU sensor temperature which changes too fast. This change is based on the discussion on bug:235311241 comment#7. BRANCH=firmware-brya-14505.B BUG=b:235311241, b:261749371 TEST=Built and tested on Skolas system Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71692 Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/skyrim: Disable keyboard resetMartin Roth
The keyboard reset is not being used on this board, so disable the functionality. BUG=None TEST=Check register values Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4a9f8f254dfefcb32a77f558f984bcdd6004d34b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72913 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10mb/google/poppy/rammus: Fix NHLT initMatt DeVillier
Commit bf3c648fa7f6 ("soc/intel/skl; mb/google/eve,poppy: Update NHLT methods") contained a copy/paste error for rammus, swapping the max98373 entry for the correct max98927 one. Change it back. TEST=build/boot Windows on rammus, verify audio functional with coolstar's AVS audio drivers. Change-Id: Ibcd4b752e01866a3dd54997f1d2a6c079b07b7a3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/volteer/drobit: Add missing TBT devicetree entriesMatt DeVillier
Commit ae20d4c78f9f ("mb/google/volteer: Fix USB4 enabling for volteer family") reworked the USB4/TBT config for volteer, but drobit variant was missed for some reason. Add the missing USB4/TBT entries. TEST=build/boot Windows on drobit, verify USB4/TBT functional. Change-Id: I43d771eeaf29b4e141b222ccb05af5cb7ceedc6f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/hatch/kohaku: Fix touchscreen power sequencingMatt DeVillier
Commit 525c61f74e94 ("mb/google/hatch: Implement touchscreen power sequencing") contained a copy/paste error; KOHAKU's enable GPIO is set twice in ramstage, and the reset GPIO not at all, leading the touchscreen to not be detected. Correct the copy/paste error by replacing the 2nd instance of GPP_C12 with GPP_D15. TEST=build/boot Windows/Linux on KOHAKU, verify touchscreen works. Change-Id: I08d35f1e2a951cdaa463daa34df2134fdc8c65c8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/drallion: Add VBT, ACPI brightness controlsMatt DeVillier
Enables display backlight control under Windows. VBT extracted from stock ChromeOS firmware Google_Drallion.12930.543.0. TEST=build/boot Win11 on drallion, verify OS backlight control available and functional. Change-Id: I85065f22b825a7616fa4ac632c42ae7972091e24 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/volteer/eldrid: Fix touchscreen under WindowsMatt DeVillier
Under Win11, a longer delay after asserting reset is needed for the Goodix touchscreen to init properly. Increase the reset delay to match that used for the Goodix touchscreen by other volteer variants (120ms). TEST=build/boot Win11, Linux on eldrid variant with Goodix touchscreen, verify functional. Change-Id: I489f037f0bbade9567aad2ad64404a5ac66965d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/brya/var/constitution: Add SOLDERDOWN supportMorris Hsu
Constitution will use SOLDERDOWN. Add memory.c to override baseboard. Add mem_parts_used.txt and generate dram_id.generated.txt and Makefile.inc Memory: SAMSUNG K4U6E3S4AB-MGCL MICRON MT53E1G32D2NP-046 WT:B BUG=b:267539938 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72775 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10mb/google/brask: Add EC_HOST_EVENT_USB_MUX S0ix wake eventDerek Huang
Add EC_HOST_EVENT_USB_MUX to MAINBOARD_EC_S0IX_WAKE_EVENTS for brask. Without it EC won't send host event to wake AP when USB MUX is changed during S0ix. It's there for brya but missing for brask. BUG=b:267573651 TEST=emerge-brask coreboot Signed-off-by: Derek Huang <derekhuang@google.com> Change-Id: Id08d9aec9ab3566176369f2ca25cd00b9f0a0ca5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-02-10Revert "mb/google/skyrim: Update ASPM settings for the NVMe device"Martin Roth
This reverts commit 8e1bb93fb88bc9cc20aab33a1fe09fb4c0c652a0. Reason: Enabling L.2 breaks some devices on this bridge. Reverting until a workaround is found and additional testing is done. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9f721178244e7764e9b08e419db8a8c05ecc29a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72916 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-02-09mb/google/skyrim: Configure GPIO 67 as an unused GPIOMartin Roth
GPIO 67 is not currently used on skyrim, so set it as no-connect. Since it's now free for other purposes, make sure that the SPI-ROM-SHARING functionality is disabled. BUG=b:268330591 TEST=Examine registers after change Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id083baf41d25920eca09795453a01aac1d00d0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09mb/google/skyrim: Set system type to laptopMartin Roth
BUG=None TEST=Verify that DMI type 3 - Chassis Information Type field has changed from Desktop to Laptop Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I76c8970fe3fdc2ea322a07f114ad03a0373e152c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72907 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0Rex-BC Chen
For Geralt, we use BOE_TV110C9M_LL0 as MIPI firmware display, so add the power-on sequence for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72749 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-09mb/google/geralt: Init MT6359P only once in ramstageLiju-Clr Chen
The regulator MT6359P is needed by both firmware display and SD card. To avoid duplicate initialization in ramstage, publicize init_pmif_arb() as mt6359p_init_pmif_arb() and call it from mainboard_init(). This would save 13 ms for boot time on Geralt. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72839 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/herobrine: Enable early eMMC init in corebootShelley Chen
Move eMMC init from depthcharge into coreboot to remove it from the critical boot path. Doing so saves us almost 35ms on villager: before change: finished storage device initialization 50,783 after change: finished storage device initialization 16,255 BUG=b:254092907,b:218406702 BRANCH=None TEST=flash new FW onto villager and make sure can boot from eMMC Change-Id: I1af1ec162029120332e7f531f75c3780266d322b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/dedede/var/dibbi: Update gpio tableAmanda Huang
Config GPP_B9 as LAN_CLKREQ_ODL based on latest schematic BUG=265021899 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/brya/var/omnigul: Add SOC I2C configJamie Chen
Add SoC config and .early_init = 1 in I2C1 BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-02-09mb/google/brya/var/omnigul: Modify NVMe and UFS Storage supportJamie Chen
1. Add fw_config:STORAGE_UFS & STORAGE_NVME to switch storage. 2. rp11 off change to on. BUG:b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72090 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/skyrim/var/markarth: Override SPI flash bus speedJohn Su
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz for starting next phase. BUG=b:267539952 TEST=None Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Id46201351780bb5bc05422ff36dad6972285690e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-09mb/google/brya: Create aurash variantZoey Wu
Create the aurash variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263691099 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AURASH Change-Id: I595102778071f822c5cf69ceadeed174e5ea4836 Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72837 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815Ron Lee
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. This patch add usb_lpm_incapable config for the following variants with PS8815 retimer: - kinox MLB: C0 - volmar DB: C1 - osiris MLB: C0/C1 - mithrax DB: C1 - felwinter DB: C1 - taeko DB: C1 - gimble DB: C1 - gimble4es DB: C1 - taniks DB: C1 - marasov DB: C2 - gaelin MLB: C0/C1 - skolas DB: C1 - skolas4es DB: C1 - brya0 DB: C1 BUG=b:253402457 TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u2 disabled Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Signed-off-by: Ron Lee <ron.lee@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-08mb/google/geralt: Add support for VM18 in regulator.cSen Chu
Add regulator VM18 support to supply power for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I13bafbe10a18a18e253575fd107c9b415f28ef01 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72748 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/google/corsola: Use function to get regulator IDsLiju-Clr Chen
There might be inconsistence between regulator_id[] and `enum mtk_regulator` when we need to add new regulator IDs for Geralt. Therefore, we implement get_mt6366_regulator_id() to get regulator IDs. BUG=None TEST=build pass. Change-Id: I3d28ebf2affe4e9464b1a7c1fb2bbb9e31d64a5e Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72838 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-07mb/google/brya: Create constitution variantMorris Hsu
Create the constitution variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:267539938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CONSTITUTION Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72730 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07tree: Drop repeated wordsAlexander Goncharov
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-06mb/google/brya/var/kano: Update ELAN TS delay time to 150msDavid Wu
ELAN updated the datasheet, the HID/I2C protocol's T3 delay time is 150ms now. Modify the kano's delay time to follow the requiremnet. BUG=b:247944006 TEST=Manually checked touchscreen works after reboot and suspend. Change-Id: I42a7737060a82c0b27717f1510b8ec64abd1465a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-06soc/amd/mendocino: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Mendocino SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/cezanne: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/picasso: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Picasso SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/stoneyridge: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Stoneyridge SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Eventually the LIDS object should probably be moved to the EC's ACPI code, but that's out of scope for this patch. TEST=google/liara doesn't show ACPI errors in Linux' dmesg Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-02-05mb/google/brya/var/omnigul: Enable Cnvi BT Audio Offload featureJamie Chen
1. Enable Cnvi BT Audio Offload feature and also configure the virtual GPIO for CNVi Bluetooth I2S pads. 2. According to the SOC_GPIO_Table_20230116, Change GPIO GPP_D15, GPP_D16 to NC. BUG=b:264834572 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I4901c8cd660f2d47018e4cccdb67f666f0800423 Signed-off-by: Jamie chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72035 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-05mb/google/brya/var/omnigul: Add variant specific devicetreeJamie Chen
This variant was added without a devicetree, so add the board specific devicetree according to schematic_20230110. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-02-05mb/google/nissa/var/craask: Modify clkreq to clksrc mappingRen Kuo
NVMe PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=1,clk_req=2 in mFIT. BUG=b:265720813 TEST=build firmware and veirfy suspend function on DUT. Cq-Depend: chrome-internal:5351299 Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72051 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-05mb/google/brya/var/marasov: Turn off camera power during S0ixFrank Chu
Turn off camera power during S0ix to improve power consumption. BUG=b:265754302 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie2b300783adfc1cab30bc897d086a3674436724a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-05mb/google/skyrim/var/frostflow: Override SPI flash bus speedFrank Wu
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version of the current phase. BUG=b:260127676 TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed. Observe that the boot time improved by 100 ms compared to 66 MHz SPI flash bus speed. firmware log: SPI fast read speed: 100 MHz At 66 MHz: Total Time: 1,563,384 At 100 MHz: Total Time: 1,462,570 Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-04mb/google/skyrim: Update ASPM settings for the NVMe deviceMartin Roth
This enables L1.2 for the SSD port. link_hotplug is unused on Mendocino, so remove it while I'm here, just as code cleanup. This has no functional difference. Enabling L1.2 on other devices currently causes problems. Debug is ongoing. BUG=b:265890321 TEST=Build & boot, look at states enabled in lspci. Test device functionality. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-04mb/google/rex: Use OV13B10 sensor for Proto 1 SKUsSubrata Banik
This patch drops the WFC sensor OV8856 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor OV13B10. BUG=b:267264348 TEST=WFC MIPI cameras have been enabled using google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic785b82db4368f40d91921f29c218cf417938541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-04Revert "UPSTREAM: mb/google/rex: Enable SaGv"Subrata Banik
Enabling `SaGv` along with FSP v2473 is causing blank display issue. Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake. BUG=b:267446159 TEST=Able to see ChromeOS UI in consecutive boot. This reverts commit cbca81c5946384843197c08401c4266f45fef4a2. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-04mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:266696987 BRANCH=None TEST=Observe kernel ec panic handler run when ec panics Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-03mb/google/brya0,skolas4es,skolas: disable Tccold HandshakeSelma Bensaid
The patch disables Tccold Handshake to prevent possible display flicker issue for skolas board. Please refer to Intel doc#723158 for more information. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS on Skolas, verify upd setting. Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68636 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03mb/google/nissa/var/craask: Add DPTF settings for 15W CPURen Kuo
Add ADL-N 15W CPU thermal settings. BUG=b:265101768 TEST=emerge-nissa coreboot Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71860 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03mb/google/rex: update touchscreen report EN pin settingIvy Jian
Removed workaround since the latest schematics fixed. Power Sequencing of ELAN6918 (in ACPI) after this patch `POWER enabled -> RESET deasserted -> Report EN enabled` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-02mb/google/dedede/var/dibbi: Update devicetree and GPIO tableLiam Flaherty
Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:260934185, b:260934719 BRANCH=dedede TEST=build Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02mb/google/brya: Skip locking for GPP_F14 GPIOMaulik Vaghela
This is regarding issues observed on multiple Brya and Nissa variant such as Skolas and Nivviks. Issue is that once coreboot sets GPE_EN bit for the GPIO pin and locks it, kernel is not able to change the control bit. Hence kernel is not able to control the IRQ on the pin when required. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") This patch skips the locking for GPP_F14 to allow kernel to configure it later during reboot or shutdown as required. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas and Brya board with the patch. Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02mb/google/skolas: Skip locking for GPP_F14 GPIOMaulik Vaghela
There is an existing issue for skolas boards where board wakes up from shutdown immediately due to touchpad wake signal. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") Later issue was found to be with GPP_F14 configuration for skolas boards. While shutting down, kernel is not able to disable IRQ for touchpad due to GPE_EN register getting locked and it is preventing shutdown of the board. This patch skips the locking for GPP_F14 to allow kernel to configure it later. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas board with the patch. Nissa Bug: 234097956 Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I09cf1af1f5ab11b06073755374ee8a306984d557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72426 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/brya/var/omnigul: Add memory configAmanda Huang
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Marx Wang <marx.wang@intel.com>
2023-02-01mb/google/brya/var/omnigul: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSJamie Chen
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Omnigul variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I90ae116ccccde48792aeafaa683c7420a95c9886 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72509 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/geralt: Add USB3 HUB reset funtion to bootblockBo-Chen Chen
After powering on the device, we need to pull USB3_HUB_RST_L up to enable USB3 Hub. TEST=boot kernel from USB ok BUG=b:264841530 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31mb/google/skyrim/var/winterhold: Update DPTC settings for SMTEricKY Cheng
Follow thermal team's request on b/248086651 comment#27. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651 TEST=emerge-skyrim coreboot Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-01-30src/mainboard: Remove unnecessary space after castsElyes Haouas
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-30mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSSubrata Banik
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Marasov variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. Note: Enabling this config would introduce an additional warm reset during the cold-reset scenarios due to the function disabling of the UFS controller as results we are expecting ~300ms higher boot time (which might not be user visible because `cbmem -t` can't include impacted boot time due to in-between resets). BUG=b:264838335 TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS during boot path. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-25mainboard: Drop invalid `hyper_threading` optionAngel Pons
Drop the `hyper_threading` CMOS option from most boards, as it's most likely not working properly and causing problems. The main reasons to remove the option are: * The used enum is backwards (0 ---> Enable, 1 ---> Disable) * Platform/SoC code does not honor the `hyper_threading` option Also, remove the now-unused enum used by the `hyper_threading` option. Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-25mb/google/skyrim/baseboard/devicetree: enable mp2 deviceFelix Held
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. An equivalent change was verified on Chausie. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-22mb/google/brya: Add lp5x memory parts for CrotaTerry Chen
Update the mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign MT62F1G32D2DS-026 WT:B 4 (0100) K3KL8L80CM-MGCT 4 (0100) H58G56BK7BX068 4 (0100) BUG=b:259467147 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I204e871129a1b15d7c373d579e10a7b9ab6deabe Reviewed-on: https://review.coreboot.org/c/coreboot/+/71906 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-22Revert "mb/google/brya: Add EC mux device to brya0"Anil Kumar
This reverts commit 197d550d069f918698fa7cd8dda73e09fbfda30c. Reason for revert: breaks TBT and TypeC display on Brya0 Bug=265375098 Branch=firmware-brya-14505.B Test=Build and boot Skolas board with Brya0 image. Test TBT and TypeC display functionality. Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081 Reviewed-by: Prashant Malani <pmalani@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-20mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMSTarun Tuli
1) Update location of TGP (MAGA) to Params2[15:0] 2) Add TPPA (value of 25W) Package: ... Case (0x02) { Local0 = Buffer (0x31) { 0x22, 0x05, 0x10, 0x1C, 0x01 } CreateWordField (Local0, 0x1D, MAGA) CreateWordField (Local0, 0x19, TPPA) CreateDWordField (Local0, 0x15, CEO0) MAGA = 0x50 TPPA = 0xC8 CEO0 = 0x0200 Return (Local0) } ... BUG=b:214581372 TEST=build and verify DSDT on device Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69639 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency and hold time to meet touchpad i2c SPEC. - Frequency: 380 ~ 400 kHz - hold time : 0.3 ~ 0.9 us BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 393.7 kHz Hold time = 0.604 us Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/google/brya/var/gaelin: Add touch panel module settingMike Shih
1. Enable multiple GPIOs to support the touch panel. 2. Add I2C setting for touch panel. BUG=b:260818082, b:264812909 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Change-Id: I2b805d1960f8b4e3e27f1af02f9c4d31f973288f Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-01-19intel/meteorlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for ChromeOS platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19mb/google/skyrim/var/frostflow: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for frostflow in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259007881, b:248221908 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19mb/google/skyrim/var/markarth: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for markarth in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:263534907, b:263216451 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-01-18mb/google/brya/var/marasov: Remove wlan RTD3 supportFrank Chu
Wlan power enable pin is changed from EN_PP3300_WLAN to SLP_SUS_L. Remove unused RTD3 driver. BUG=b:263448873 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I22448a8cb28ddadb93b114c096e364980feab6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71693 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18mb/google/skyrim: Add custom amdfw.cfg file to remove fwTPMMartin Roth
Skyrim doesn't use the firmware TPM, so remove the binary from the image. Note that because this was not used, removing it doesn't change the boot time. BUG=None TEST=Boot Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia627b128c3346a2556c5306de7506519d1f2d70c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17mb/google/skyrim: Set winterhold SPI fast read speed to 100MHzMartin Roth
Winterhold runs with the SPI fast read speed set to 100MHz. This decreases boot time by roughly 100ms. BUG=None TEST=Examine boot times. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 21:47:51 +0000