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path: root/src/mainboard/google/veyron_rialto
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2015-04-28Kconfig whitespace fixesMartin Roth
trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEXAaron Durbin
These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22google/veyron_rialto: support the developer key GPIOJonathan Dixon
Currently (EVT) this is a pullup resistor on the board (i.e. always in dev mode). Future builds it will be pull down and require servo or HW modification to control. Either way, this change means the FW should acknowledge it. BUG=chrome-os-partner:38663 TEST=Manually verified that servo devmode switch toggles this GPIO. requires FW signing to verify GPIO is observed and dev mode active. BRANCH=none Change-Id: Ib05216992abc5f6175fe7395471bd379f185b61f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 702c8d222a3d19d6b8db89d122dcdf594c85da99 Original-Change-Id: I1d0f31819b9f7a1ab63deac52bcaf0b996499b0c Original-Reviewed-on: https://chromium-review.googlesource.com/263529 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Jonathan Dixon <joth@chromium.org> Original-Commit-Queue: Jonathan Dixon <joth@chromium.org> Reviewed-on: http://review.coreboot.org/9928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22switch mainboards over to use BOARD_ID_AUTOStefan Reinauer
This patch switches the mainboards with board id straps to use BOARD_ID_AUTO instead of BOARD_ID_SUPPORT. On urara, which does not have those straps, the option is removed. (And re-added for urara derivatives through setting the config option BOARD_ID_MANUAL BRANCH=none BUG=chrome-os-partner:37593 TEST=emerg-nyan_big coreboot, emerge-urara coreboot, emerge-buranku coreboot Change-Id: I5ac4024c6f1f9b9d7a5179d88722c69b23b82bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 22a470698f9c9ed275aa8150a5bb8d8cf368b050 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Change-Id: I48c291ad6f255a28c833bebc2638bfafa2782e74 Original-Reviewed-on: https://chromium-review.googlesource.com/262935 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9906 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_*: Increase SPI flash frequency to 24.75MHzJulius Werner
This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288 (veyron) boards. This increases flash read speeds (and thereby decreases boot time) significantly, but we don't seem to get any more increases by going even higher. We have also seen occasional read failures at higher speeds in certain configurations, so this frequency seems to be the best option. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Booted on Jerry with Servo attached. Change-Id: I9bdb62eff169fe2be33558caafe9891668589372 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262645 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: Fix SPI clock divisor calculationJulius Werner
The code to calculate the RK3288 SPI controller's internal clock divisor is wrong: it assumes that the divisor register was an "n-1" divisor when it actually isn't (due to some misleading kernel code that was copied in here). This means that all SPI clocks are currently running lower than expected. This patch fixes the calculation and changes all callers such that the effective speeds stay the same. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Booted Jerry with and without the patch, dumping the divisor for flash and EC clocks. Made sure it stays the same. Change-Id: I2336e2b81c2384b5076175fcf32717a3ab2ba0c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1fd5b990f937019a9bee7bd693c91d6e2fca1adb Original-Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262269 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron: The ODT function is disabled for LPDDR3jinkun.hong
We found that we should better keep ODT off for LPDDR3 on our boards. BRANCH=veyron BUG=chrome-os-partner:37346 TEST=Boot veyron_speedy normal Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599 Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255381 Reviewed-on: http://review.coreboot.org/9830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-20Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UARTPatrick Georgi
Some upstreaming patches missed that, so follow up. Change-Id: I28665c97ac777d8b0b0f909e64b32681ed2b98f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9771 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-17veyron_{brain,danger,rialto}: Enable eventloggingDavid Hendricks
This brings brain, danger, and rialto up to parity with other veyron platforms as far as eventlog functionality is concerned. BUG=chrome-os-partner:34436 BRANCH=none TEST="mosys eventlog list" shows events (tested on Brain) Change-Id: I186c5d18e5351c0eaf08ffecfd87506283c44b19 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1764bc53147718031231a6d125a4a1a96c4c6a8f Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ief09299965f6f21bc5a40cef31cde61344025c2a Original-Reviewed-on: https://chromium-review.googlesource.com/239979 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron_{brain,danger,rialto}: Use common watchdog rebootDavid Hendricks
This applies a previous patch ("chromeos: Provide common watchdog reboot support") to some veyron platforms that were missing it. BUG=none BRANCH=none TEST=built and booted on Brain Change-Id: I3eb431a57367b8f885844e4353a78f77515f5195 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b0c87dd4217917a35817c719efe43dd4ec442df0 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I2861939655a995d309847f64cecd974a740fae37 Original-Reviewed-on: https://chromium-review.googlesource.com/245633 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: detect sdram size at runtimehuang lin
we use Kconfig define sdram size before, but there may use different sdram size in the same overlay, so we must detect sdram size at runtime now. If we use 4G byte sdram, we can use[0x00000000:0xff000000], since the [0xff000000:0xffffffff] is the register space. BUG=chrome-os-partner:35521 TEST=Boot from mighty BRANCH=None Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898 Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243139 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron: move setup_chromeos_gpios() prototype to board.hJulius Werner
I always had that TODO comment in there but I had already forgotten what I even meant by it. It's really just a simple cleanup... this function is (currently) veyron-specific and doesn't belong in common code. BRANCH=veyron BUG=None TEST=Booted Jerry. Change-Id: Iccd6130c90e67b8ee905e188857c99deda966f14 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d188398704575ad2fedc2a715e609521da2332b0 Original-Change-Id: I6ce701a15a6542a615d3d81f70aa71662567d4fa Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241190 Reviewed-on: http://review.coreboot.org/9733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15veyron_rialto: Change recovery GPIO to PUSH_KEY.Hung-Te Lin
The recovery button on Rialto should be GPIO 255, the LED Push Key. Note we want to keep the recovery button on servo functional because many protos are not assembled and developers can't "push" the push key. The GPIO passed to payloads (and kernel) is only mapped to Push Key. BUG=none TEST=emerge-veyron_rialto coreboot chromeos-bootimage BRANCH=veyron_rialto Change-Id: I66f94cf232caa53a3b28db517620e4b6e9b9af0e Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 66ee55f6312efaeb337eb2881cd5eff5365b4105 Original-Change-Id: I0a7ebeed6506fbd938084c9a078a7cf1c7b914b9 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/244515 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15veyron_rialto: Fix boot failure in romstage.Hung-Te Lin
The FMAP for Rialto has no ecrwhash and would cause verstage to incorrectly load ramstage (instead of romstage) when looking for subsection inside RW blob. We have to override the index of stages to boot correctly. BRANCH=veyron_rialto BUG=none TEST=emerge-veyron_rialto coreboot chromeos-bootimage Boots successfully on Rialto boards. Change-Id: I031703d97a68e42dc17630ab5df85f8cba47e5e5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 24ba4b16b4a2fe5469296f8d40286ed926cefc3c Original-Change-Id: I637ea23e1e8265781e52367d1306dbf854c2ccad Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/244577 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-15veyron: Add veyron_rialto boardjinkun.hong
Derived from of veyron_brain with new memory configuration. BUG=chrome-os-partner:35072 TEST=built and boot on rialto-rev0 boards. BRANCH=veyron Change-Id: I2c6f74d231e39de76ef2399fdb20efae977b34fa Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 17d66e5f58562427badd6973ebb053f58573c040 Original-Change-Id: I8626ff5da8098ca120481b8cda0c6703f806711e Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238946 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Trybot-Ready: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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