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path: root/src/mainboard/google/skyrim
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2023-12-20treewide: Use show_notices target for warningsMartin Roth
This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-17mb/google/skyrim: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the blobs repository; it is simply being relocated for consistency and since it does not need to be in an external repo. BUG=none TEST=build/boot skyrim Change-Id: I352f58e0d3965356f3282a2653c6c11b44853857 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-11-16mb/google/skyrim/frostflow: Drop GPIO override for camera shutterMatt DeVillier
Appears to not be used under Windows, Linux, or ChromeOS, and causes high CPU usage at idle under Windows. BUG=none TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter function unchanged, CPU usage under Windows idles where expected. Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-28mb/google/skyrim: Clean up Kconfig entriesMatt DeVillier
Alphabetize board entries, Kconfig selections, and config options. Reverse default logic of PERFORM_SPL_FUSING for simplicity / clarity. Change-Id: Ib25bb8c7bbf994f2f0675c4599c70a7db5d9f7ef Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-28mb/google/skyrim/Kconfig.name: Alphabetize entries, add namesMatt DeVillier
Alphabetize entries and add consumer product names for boards where available. Change-Id: I7459ee0a63025c12c7dbe75c578c7496c49fa475 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-25soc/amd/*/Kconfig: rework SPL optionsFelix Held
Move all security patch level (SPL) related Kconfig options to the common AMD PSP Kconfig file. Commit 4ab1db82bb30 ("soc/amd: rework SPL file override and SPL fusing handling") already reworked the SPL handling, but missed that another Kconfig option SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL controlled if the PSP mailbox command to update the SPL fuses was sent by the code that got added to the build when PERFORM_SPL_FUSING was selected. To make things less unexpected, rename PERFORM_SPL_FUSING to SOC_AMD_COMMON_BLOCK_PSP_SPL since it actually controls if the SPL support code is added to the build and also rename SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL to PERFORM_SPL_FUSING. This changes what PERFORM_SPL_FUSING will do from including the code that could do the fusing if another option is set to being the option that controls if the fusing mailbox command will be set. All SoCs that support SPL now select SOC_AMD_COMMON_BLOCK_PSP_SPL in their Kconfig, which won't burn any SPL fuses. The logic in the Skyrim mainboard Kconfig file is reworked to select PERFORM_SPL_FUSING for all boards on which the SPL fuses should be updated; on Guybrush PERFORM_SPL_FUSING default is changed to y for all variants. The option to include the code that checks the SPL fusing conditions and allows sending the command to update the SPL fuses if the corresponding Kconfig is set doesn't need to be added on the mainboard level, since it's already selected at the SoC level. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12fd8775db66f16fe632674cd67c6af483e8d4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-24mb/google/skyrim/var/crystaldrift: Update the STT settingsYunlong Jia
Adjust the STT settings. BRANCH=none BUG=b:270112575 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1df9bbf820b5a760007dcfd7bceb21063fc24696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78523 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-10-04soc/amd: rework SPL file override and SPL fusing handlingFelix Held
The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a way to override the default SPL file configured in the SoC's fw.cfg file by passing the '--spl-table' parameter to amdfwtool which will then use the override instead of the SPL file from the fw.cfg file. When SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix call in the makefile will result in no '--spl-table' parameter being passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In order to not pass an SPL override by default, remove the default from the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the same SPL file as in fw.cfg file anyway. Now only when a mainboard sets this option to point to a file, that file will be used as an override. This override is used to include a special SPL file needed for the verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an empty string by default, neither the SPL_TABLE_FILE Kconfig option nor it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE, so remove the dependency in the Kconfig and the ifeq in the Makefile. Before this patch, the HAVE_SPL_FILE option controlled two things that shouldn't be controlled by the same Kconfig option: Only when HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into account, and it also controls if spl_fuse.c got added to the build which when added will send the SPL fusing command to the PSP. So the case of needing an SPL file override, but not updating the SPL fuses wasn't supported before. The SPL file in the amdfw part will be used by the PSP bootloader for the anti-rollback feature which makes sure that the SPL file version isn't lower than what is in the SPL fuses. For this the SPL file needs to be present in the PSP directory table. The SPL version check happens way before we're running code on the x86 cores. The SPL fusing PSP command that can be sent by coreboot will tell the PSP to update the SPL fuses so that the fused minimal SPL version will be updated to the current SPL version. Since the former HAVE_SPL_FILE option now only controls if the SPL fusing command will be sent to the PSP mailbox, rename it to PERFORM_SPL_FUSING to clarify what this will do and update the help text correctly describe what this does. TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman with Phoenix APU and Skyrim result in identical binaries. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/78178 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02security/tpm: Enable Hibernate on setup failureJon Murphy
Set default to enabled for hibernate on setup failure for all devices using a Google EC. This will have no impact on devices that don't bring the GSC down on hibernate, but will provide a recovery path for all devices that do. BUG=b:296439237 TEST=Force error on Skyrim with custom build, boot normally with normal build Change-Id: I2d9e8f75b25fb6c530a333024c342bea871eb85d Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78098 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/skyrim: Enable hibernate on TPM errJon Murphy
Enable hibernate on TPM setup error for Skyrim devices. BUG=b:296439237 TEST=Force the error by hard coding the return code and observe the device entering hibernate. BRANCH=None Change-Id: Ibf96b830f07dac98035d3152c8ec220685a912bc Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77668 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/skyrim/frostflow: Hide fingerprint reader from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on frostflow, verify unknown device for the fingerprint reader no longer present. Change-Id: I666e92706f698608f2df92c8296cfb615d5ece67 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21mb/google/skyrim: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I097d50a7af7c8ea48369806e8bb73734a8e84470 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75024 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mainboard/google/skyrim: Enable wake-on-DPRobert Zieba
Enable wake-on-DP by adding USB mux events to the wake mask. The EC wakes the AP with these events for DP connect/disconnect. BUG=b:294307786 TEST=DP connect/disconnect wakes the DUT appropriately. Change-Id: I864b03d08ce3d756bf4987d886db621d937483ce Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78034 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-18mb/google/skyrim: Re-enable USE_SELECTIVE_GOP_INIT for SkyrimMatt DeVillier
This reverts commit dc7cc5bc6edf ("mb/google/skyrim: Disable USE_SELECTIVE_GOP_INIT") but limits the default enablement to Skyrim variant only, to allow for continued testing. BUG=b:271850970 BRANCH=skyrim TEST=build/boot ChromeOS R117+ on google/skyrim, verify no display init failures with feature enabled on cold/warm boots or S0i3 resume. Change-Id: I21c70111a5f407a7e8dd1ad1f2c2759ddb91893e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-11mb/google: Remove space between function name and '('Elyes Haouas
Change-Id: I0909f24844fab3dfc859ea8c5325344a9872799f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07mb/google/skyrim: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: Idb5d2cd6eca2a2746e89a371005332e9f621df83 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77675 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01mainboard/google/skyrim: Enable MP2 FW loadingRobert Zieba
This board will use custom MP2 FW to dump the contents of the STB when the SOC fails to enter/exit S0i3. Enable `PSP_LOAD_MP2_FW` by default. BUG=b:259554520 TEST=Built and ran on skyrim device, verified that MP2 FW loads. Change-Id: I4222521d01e2c98708f0e5b6693a8aee9e59edf2 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72118 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-21mb/google/skyrim/var/crystaldrift: drop commented out line in DTMatt DeVillier
Line is a duplicate, commented out. Drop it as it serves no purpose. Change-Id: Id35bdea0915ca47cac4f38ede6ccbf2f2fb59f47 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77304 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/skyrim: Enable SPL fusing on crystaldriftYunlong Jia
Enable Crystaldrift platform to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499517 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1d41505e64bf54ad911ad7d287263013a9c458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-04mb/google/skyrim: Select ACPI_S1_NOT_SUPPORTEDTim Van Patten
As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby. The wake issue either needs to be fixed, or S1 should not be advertised as a capability in the ACPI table. Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not supported on Skyrim devices. This results in 'standby' being removed from /sys/power/state. BUG=b:263981434 TEST=suspend_stress_test TEST=frostflow-rev2 ~ # cat /sys/power/state freeze mem Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-14mb/amd,google/*/port_descriptors: use dxio_link_hotplug_type enum valuesFelix Held
Use the proper dxio_link_hotplug_type enum values for the link_hotplug field in the DXIO descriptors to replace the magic values in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14mb/google: AMD: move tpm_tis to AMD common codeGrzegorz Bernacki
It moves cr50_plat_irq_status() to common code and adds Kconfig option to specify GPIO used for interrupt. BUG=b:277787305 TEST=Build all affected platform and confirm using right GPIO number. Tested on Skyrim. Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-07mb/google/skyrim/var/crystaldrift: Override SPI flash bus speedYunlong Jia
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz for starting next phase. BUG=b:270500631 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0915d9b10dbfae7fff4e8874011951d1690de870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-28mb/google/skyrim/var/winterhold: Set system_configuration to 3 to avoid SMU callJason Glenesk
Update system_configuration to 3 for 15W. Specification "FT6 Infrastructure Roadmap #57316" incorrectly lists system config index of 4 for 15W. Setting to 4 will cause an additional call to the SMU that is not needed and will add boot delay. Both SMU and FSP interpret configs > 3 as 3. BUG=b:267294958 TEST=Confirm extra message "Service Request 0x5F" not in log. Change-Id: Ib12c73f95030625b52e26f86e932ee2aaa6ea522 Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-28mb/google/skyrim/: Set system_configuration to 3 to avoid SMU callJason Glenesk
Update system_configuration to 3 for 15W. Specification "FT6 Infrastructure Roadmap #57316" incorrectly lists system config index of 4 for 15W. Setting to 4 will cause an additional call to the SMU that is not needed and will add boot delay. Both SMU and FSP interpret configs > 3 as 3. BUG=b:267294958 TEST=Confirm extra message "Service Request 0x5F" not in log. Change-Id: I1f3e305c48801b4e499de56d06c0dcd3eeacc626 Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76091 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-06-14mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAMMatt DeVillier
One specific Hynix LPDDR5x DRAM part requires an ABL workaround to eliminate DRAM-related failures during a FAFT test, but due to the use of generic/common SPDs, there is no way for the ABL to determine the DRAM part # itself. Consequently, we will have coreboot check the DRAM part #, and set/clear a CMOS bit as appropriate, which the ABL will check in order to apply (or not apply) the workaround. The ABL already uses byte 0xD of the extended CMOS ports 72/73 for memory context related toggles, so we will use a spare bit there. BUG=b:270499009, b:281614369, b:286338775 BRANCH=skyrim TEST=run FAFT bios tests on frostflow, markarth, and whiterun without any failures. Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2023-06-09soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetreeFelix Held
Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. TEST=SSDT entries for the XHCI controllers are still generated on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-31mb/google/skyrim: Add common_config.acp_configTim Van Patten
Add 'common_config.acp_config' to the device tree, so we have the correct pin configuration. BUG=b:225320579 TEST=USE=fwconsole emerge-skyrim ... ; verify 'devbeep' works in depthcharge console TEST=Boot into ChromeOS, verify YouTube sound works with internal speakers and headphone jack TEST=Boot into ChromeOS, verify microphone with Google Meet Change-Id: Ie2d79408104273d8a53214b683800fa0663c14d3 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-25mb/google/skyrim/var/winterhold: Fix USB port register scopeMatt DeVillier
Commit f99d6700 ("mb/google/skyrim/var/winterhold: Fix USB port ACPI generation") fixed the USB-A ports being double-nested, but neglected to move the chip driver registers up into the correct scope. While the generated ACPI is still correct, fix the register scope anyway to avoid confusion. BUG=b:283778468 BRANCH=skyrim TEST=build/boot winterhold, dump ACPI, verify unchanged Change-Id: Ia9982fed0fe2093d787ee9506ac5bbadd6cc03f9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75389 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25mb/google/skyrim/var/markarth: Fix USB port register scopeMatt DeVillier
Commit d81ee3f1 ("mb/google/skyrim/var/markarth: Fix USB port ACPI generation") fixed the USB-A ports being double-nested, but neglected to move the chip driver registers up into the correct scope. While the generated ACPI is still correct, fix the register scope anyway to avoid confusion. BUG=b:283778468 BRANCH=skyrim TEST=build/boot markarth, dump ACPI, verify unchanged Change-Id: I5c1cd23c49b512f55e9e13b2164d30dfb7fb682d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75388 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25mb/google/skyrim/var/frostflow: Fix USB port register scopeMatt DeVillier
Commit a539893c ("mb/google/skyrim/var/frostflow: Fix USB port ACPI generation") fixed the USB-A ports being double-nested, but neglected to move the chip driver registers up into the correct scope. While the generated ACPI is still correct, fix the register scope anyway to avoid confusion. BUG=b:283778468 BRANCH=skyrim TEST=build/boot frostflow, dump ACPI, verify unchanged Change-Id: I3912fe1b7d3f2a07cb379928cd4f5d87100d3284 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75387 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-23mb/google/skyrim/var/winterhold: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=untested, but same error/fix as frostflow variant. Change-Id: Ic498afcc8b8e0224f344f405e2f1ef6184df1d6b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75340 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/skyrim/var/markarth: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=untested, but same error/fix as frostflow variant. Change-Id: Ie40541ada508acfa5771ea800249b8a57b168e3b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/skyrim/var/frostflow: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=build/boot frostflow, verify error no longer present in dmesg. Change-Id: I0b87af6b2c04f9354e6f394a8f987fa660e49134 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75338 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/skyrim/var/markarth: Update DPTC and STT settingsJohn Su
According to Thermal table 0518, adjust DPTC and STT settings. BRANCH=none BUG=b:273636128 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-05-22mb/google/skyrim: Enable DmaProperty on WLAN deviceMark Hasemeyer
Set the DmaProperty in the device's _DSD so that the OS can treat the device as untrusted. BUG=b:278310256 TEST=cat /sys/bus/pci/devices/<wifi>/untrusted == 1 iperf3 -c <iperf3-server> -t 60 (No performance regressions seen) Change-Id: I06369a19afa5b881b26f5c1eb243e2db41a9bb36 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75095 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-03Drop many cases of CONFIG_MAINBOARD_PART_NUMBERKyösti Mälkki
We have largely dropped from filling in mainboard_ops.name as unnecessary. A common place should be decided where or if this information is added in the console log. Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-28mb/google/skyrim: Enable SPL fusing on MarkarthJohn Su
Because SPL fuse needs to be set before the FW lock. So enable Markarth project to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499511 BRANCH=none TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27mb/google/skyrim/var/winterhold: Add support for K3KL6L60GM-MGCTRex Chou
Update Samsung 4G K3KL6L60GM-MGCT support BRANCH=None BUG=b:243337816 TEST=emerge-skyrim coreboot Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27mb/google/skyrim/var/winterhold: adjust the eDP panel power sequenceChris Wang
Set edp_panel_t9_ms to 8ms which means it will delay 8ms between backlight off and vary backlight off. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was passed to system integrated table; Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_msChris Wang
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq insteadEricKY Cheng
Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:274377518 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-26mb/google/skyrim: Disable unused SPI ROM typesMartin Roth
By default, coreboot includes support for all the different types of SPI ROMs. Excluding the unused ROM types shrinks ramstage by almost 4k. BUG=b:267735039 TEST=Build & Boot ROM BRANCH=Skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72769 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-22soc/amd/mendocino: drop code for non-existing eMMC controllerFelix Held
Mendocino and Rembrandt don't have an eMMC controller and also don't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-21mb/google/skyrim/var/markarth: Change to read the eMMC clkreq insteadJohn Su
Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:278495684 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74583 Reviewed-by: Chao Gui <chaogui@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-19mb/google/skyrim: Fix eMMC reset GPIOJon Murphy
On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6). Update the port_descriptors to link the correct reset GPIO. Data is from the skyrim variant schematics and go/skyrim-gpios. BUG=b:278759559 TEST=reboot: 5 iterations suspend_stress_test: 10 iterations Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74512 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12mainboard/google/skyrim: Fix MP2 FW namingMarshall Dawson
Update the blob type for TypeId0x25_Mp2Fw_MDN_AD03.sbin to subprogram 0. Delete the extra MP2FW line. BUG=b:246770914 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I5418b1ed59e1916b971d2eece9f6a2fd0e51b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-12mb/google/skyrim: Remove mainboard LIDS ACPI objectKarthikeyan Ramasubramanian
With EC's lid switch implementation, there is no need to maintain the lid switch state in mainboard. Hence remove LIDS ACPI object from mainboard. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Read the lid switch state correctly through /proc/acpi/button/lid/LID0/state. Change-Id: I0f8dc7216337268c421a475f54ee5b28abf33d08 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11mb/google/skyrim: Enable UPD usb3_port_force_gen1 for MarkarthJohn Su
From request, all type C port limit to to Gen1 5GHz. So enable UPD usb3_port_force_gen1 for Markarth. BUG=b:273841155 BRANCH=skyrim TEST=Build, verify the setting will be applied on Markarth. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I9314b67a82ad2993c87f0110db5ec927caaa772b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74087 Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06mb/google/skyrim: override Markarth PCIe configJohn Su
Because Markarth PCIe port 1 use for eMMc not SD. So we need override PCIe config for Markarth. And also the Markarth have NVMe and eMMC SKU. Follow Winterhold to look at the NVMe CLKREQ signal before initializing the ports allowing us to identify which device is populated and only initialize that device. BRANCH=none BUG=b:275669215 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74133 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-05mb/google/skyrim: Remove unused sleep GPIO tableKarthikeyan Ramasubramanian
On Skyrim, there isn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function overhead. BUG=None BRANCH=Skyrim TEST=Build Skyrim BIOS image. Change-Id: Ia9d55a5e2295bb2e2c2957c4f5207362f616022c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-31mb/google/skyrim: Disable L1.2 for SD portMartin Roth
Having L1.2 enabled on the SD port increases the kernel resume times by between 30 & 40ms. This patch disables L1.2 on SD to get that time back. As with needing to have hotplug enabled on the SD card, this seems like a driver issue, so hopefully that will get sorted out and this patch can be reverted. BUG=b:274025743 TEST=resume times are decreased. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2c409fa2cd66c712c5ba7104635499d63fa0d2be Reviewed-on: https://review.coreboot.org/c/coreboot/+/74118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-30mb/google/skyrim: Use die_no_apcbFred Reitberger
Use die_no_apcb to cause a build error when the APCB or SPD sources are not found. TEST=builds with and without matching APCB and SPD sources Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I62dce2c71061bfc5c01e0344b7dc115a47669140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/skyrim: Get ready to add MP2 firmwareMartin Roth
This sets the location of the skyrim MP2 firmware within the mainboard's blobs directory, and adds the Kconfig option to the mainboard directory so that it can be enabled in a saved .config file. The skyrim MP2 firmware is skyrim specific, so it should not be placed in the main PSP AMD_BLOBS directory. We will also only want to enable the MP2 firmware for chromeos builds as it's not useful for non-chromeos builds. BUG=b:259554520 TEST=Build MP2 firmware into image, see that it gets loaded BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I04be6f2d0b605d4eca37fd927a70310259dc106c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-29mb/google/skyrim/var/winterhold: adjust the eDP panel power sequenceChris.Wang
set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms between backlight on and vary backlight. BUG=b:271704149 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27mb/google/skyrim: Add UPD usb3_port_force_gen1 for skyrimPatrick Huang
Add UPD usb3_port_force_gen1 for skyrim The default setting is set to disable Skyrim -> set default as disable BUG=b:273841155 BRANCH=skyrim TEST=Build, verify the setting will be applied on skyrim. Change-Id: Id53bed82a9fef93b574c3f30830555e02d7f4737 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-23mb/google/skyrim: Re-enable hotplug for SDMartin Roth
It seems like the hotplug enable might be doing more than just enabling devices to be hot-plugged, so re-enable the feature for the SD card. Removing it from SD increased resume time and may have caused reboot issues for SD after resume. This is a partial revert of CB:73512 BUG=b:273620322 TEST=See resume time go down on Skyrim BRANCH=Skyrim Change-Id: I4814d4377d0ba8a1e9b308853b3e02a4a27bd8d5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73868 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-23mb/google/skyrim: Enable SPL fusing on frostflowFrank Wu
Enable Frostflow platform to send the fuse SPL (security patch level) command to the PSP. BUG=b:274028833 BRANCH=none TEST=FW_NAME="frostflow" emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Change-Id: I6437d5324877702f2f8b4c69d4c850543e1b74be Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73884 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-22mb/google/skyrim: Remove todo about BT controller timeoutsMartin Roth
This will be tracked directly in the bug, so a code comment is not needed. BUG=263161283 TEST=none BRANCH=Skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4d5af35762354c8825d30f813098547a7e009e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73828 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-21mb/google/skyrim: Remove TODO about moving AMDFWMartin Roth
We're not going to move the AMDFW binary around at this point, so get rid of the TODO. BUG=None TEST=None BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If802c3ee19f4e6a3a74da49bbda55f6a89fa8060 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73827 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-03-21mb/google/skyrim: Delete PSPP TODOMartin Roth
Because Mendocino doesn't support PCIe Gen4, PSPP on this platform does not save any power, so leave it disabled. BUG=273889287 TEST=None BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1a1c6692cd0a44469a35582042b92eeec31073fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-20mb/google/skyrim/var/winterhold: Update DPTC settings for final versionEricKY Cheng
Follow thermal team's request on b/248086651 comment#32. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651,b:241180483 TEST=emerge-skyrim coreboot Change-Id: Ibcf6c110029d39bdc6bfaf46c234a4073ee69f30 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-17mb/google/skyrim/var/crystaldrift: Add 1 Micron parts to RAM ID tableYunlong Jia
Add new memory MT62F2G32D4DS-026 WT:B to replace H9JCNNNBK3MLYR-N6E. Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) MT62F2G32D4DS-026 WT:B 3 (0011) K3LKBKB0BM-MGCP 4 (0100) BUG=b:273177939 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I545bd8d9f88e7b3055acef4066769e6fcb766cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73681 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15mb/google/skyrim: Do not pass recovery APCBKarthikeyan Ramasubramanian
If recovery APCB is not passed, amdfwtool will build amdfw*.rom with AMD_BIOS_APCB_BK entry pointing to the same offset as AMD_BIOS_APCB entry. This will help to save 40 KiB flash space in each FW slot. On ChromeOS, this means saving ~120 KiB flash space. BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Change-Id: Ib3bbc1eededae20b2cd48f514722a207c46536a0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73662 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-14mb/google/skyrim/var/frostflow: Update the STT settingsFrank Wu
According to file thermal_table_0310, adjust the STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Change-Id: If4500c85dcea051aca15602f1fb4b5ec80b73e67 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-03-13mb/google/skyrim/var/winterhold: Change touch controller T3EricKY Cheng
Change stop_delay_ms time(T3) from 180 to 150 to meet specification. T3 min-value of HID-I2C should be 150ms. BUG=b:267280863 TEST=emerge-skyrim coreboot chromeos-bootimage. Change-Id: I7ef7db4edaecece1fa5ab07e30a80e556ed35f8b Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-10mb/google/skyrim/var/markarth: Add 2 Micron parts to RAM ID tableJohn Su
Add new ram_id:0011 for Micron MT62F1G32D2DS-023 WT:B. Add new ram_id:0100 for Micron MT62F2G32D4DS-023 WT:B. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) MT62F1G32D2DS-023 WT:B 3 (0011) H58G66BK8BX067 4 (0100) MT62F2G32D4DS-023 WT:B 4 (0100) BUG=b:271188237 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I59a6a6dff249cd4fe982a4de824848f1bac0ecba Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73510 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10Revert "mb/google/skyrim: Create whiterun variant"Jon Murphy
For simplicity, OEM devices are given a single codename per build variant. Winterhold was intended to be the lead device and was chosen as the code name for this OEM. Unfortunately, Winterhold was cancelled. We attempted to rename Winterhold to Whiterun to avoid future confusion. Again, unfortunately, since some devices were already built, changing the name requires a manual change to force the firmware to be taken by the DUT. This was not a reasonable path forward, so we're abandoning the naming to Whiterun. This reverts commit af69de494e2c32140ce5e00a1562c2845345b1bf. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idef95f0f4f369b235937e1806ce57c427e441f21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73583 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-09mb/google/skyrim: Store XHCI PCI resourcessRobert Zieba
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. Example elog contents: ``` 244 | 2022-10-11 15:49:24 | S0ix Enter 245 | 2022-10-11 15:49:29 | S0ix Exit 246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31 247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256 248 | 2022-10-11 15:50:08 | S0ix Enter 249 | 2022-10-11 15:50:16 | S0ix Exit 250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31 251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BUG=b:186792595 TEST=Ran on skyrim proto, verified that wake events show in elog Change-Id: I529f541a8932267a8825773ddc582beafb27da63 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68325 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/google/skyrim: override winterhold PCIe configMartin Roth
Winterhold boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09mb/google/skyrim: drop link_hotplug from port descriptorsMatt DeVillier
These ports are not hot pluggable, so drop the parameter, which will result it in being set to zero / not enabled. BUG=none TEST=build boot skyrim, verify all PCIe devices functional. BRANCH=skyrim Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Enable L1 ASPM substates for PCIe devicesMatt DeVillier
Enable both L1.1 and L1.2 substates for the WiFi, SD card reader, and SSD (both NVMe and eMMC). If a given device does not support a particular substate, then it will not be enabled during PCIe enumeration by coreboot. BUG=b:270690572 TEST=build/boot multiple skyrim/whiterun/frostflow SKUs with different storage configs, verify WiFi/SD card/SSD all functional and have L1 substates enabled insofar as they are supported by the device. BRANCH=skyrim Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Allow port descriptors to be overriddenMartin Roth
This allows variants to override the skyrim port descriptors. BUG=None TEST=Tested with following patches BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-08mb/google/skyrim: Enable SPL fusing on whiterun/winterholdMartin Roth
Enable whiterun/winterhold platforms to send the fuse SPL (security patch level) command to the PSP. BUG=b:254568112 TEST=On a platform that supports SPL fusing, a message indicating that fusing was requested will appear in the coreboot console log, followed by a puff of smoke when the fuse is set and the message "OK" again on the debug console. (Kidding about the smoke.) BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I45578597234ba672c89ac421b4626088faca27d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72914 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-07mb/google/skyrim: Move SPL setting to variantsChris Wang
Move the sustained_power_limit_mW setting from the baseboard to variants. This setting will be needed before STT is enabled, but once STT is enabled, this setting should be removed. BUG=b:265267957 BRANCH=none TEST=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I7b9779600cfa8c7581732e936a714728fd618d20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-05mb/google/skyrim: Disable cardbus supportMartin Roth
Skyrim does not have a cardbus socket, so disable it. Maybe cardbus support shouldn't be enabled by default? BUG=None TEST="PC Card (PCMCIA) is supported" no longer shows up in dmidecode output. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05skyrim/overridetree.cb: Remove gpio_keys ACPI nodeTim Van Patten
Only Frostflow supports the stylus, so remove the gpio-keys ACPI node from Skyrim. The Kconfig value DRIVERS_GENERIC_GPIO_KEYS is still enabled for all Skyrim variants, since coreboot will drop the driver from the BIOS image if there are no references to it (in the devicetree). If some other design ends up using the stylus in the future we won't have to bring it back. BUG: none TEST: build_packages --board=skyrim chromeos-bootimage --autosetgov Change-Id: I9ffe215741b72b678d74405769f35167d8ded4b5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-04mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0011 for Hynix H58G56BK8BX068. Add new ram_id:0100 for Hynix H58G66BK8BX067. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) H58G66BK8BX067 4 (0100) BUG=b:270629852 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73252 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-04mb/google/skyrim/var/frostflow: Update DPTC and STT settingsFrank Wu
According to thermal_table_0215, adjust DPTC and STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang
The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-03mb/google/skyrim: Disable USE_SELECTIVE_GOP_INITMartin Roth
This is causing some issues, so disable it until those issues can be resolved. BUG=b:271437658, b:271199389, b:270077971 TEST=Screen always lights up on boot & after S0i3 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-02acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-27mb/google/skryim: Add RECOVERY_MRC_CACHE FMAP sectionKarthikeyan Ramasubramanian
Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP section to cache the MRC training data in recovery mode. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS directory entry is populated with the appropriate MRC_CACHE FMAP section. Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-27mb/google/skyrim/var/winterhold: Use fw_config to probe FPEricKY Cheng
Use fw_config to probe fingerprint. BUG=b:269986245 TEST=emerge-skyrim coreboot chromeos-bootimage. Test result is pass with 1000 reboot cycles. Change-Id: I4b4bca42dd78dfd5b8636ff3cb05406d2d0c94f7 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-24mb/google/skyrim/var/winterhold: Remove gpio-keys ACPI node for PENHEricKY Cheng
Remove ACPI node for pen eject event to meet project design. BUG=b:265106657 TEST=emerge-skyrim coreboot chromeos-bootimage Change-Id: I732de49c6319397d93671c48a6518c7c7e955fdc Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73154 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-24mb/google/skyrim/var/crystaldrift: Generate RAM IDs for new memory partsYunlong Jia
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 3 (0011) BUG=b:265190498 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I860f10552e4e4180e09ab805ca82b108fdc8f21a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73049 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23mb/google/skyrim/var/crystaldrift: Update devicetree settingYunlong Jia
Setup FW_Config for our project. Configure USBHub\PIXA Touchpad\Audio(rt5682s & alc1019). BRANCH=None BUG=b:262798445, b:268621319 TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I2c590ae36d4d089f70e1799189cd414f825e5b8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-22mb/google/*: Resume from suspend on critical batteryIvan Chen
This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate when the state of charge drops to low_battery_shutdown_percent. BUG=b:255465618 TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898) Verify system resumes from s0ix and then enter S5 on nivviks with steps: 1. disconnect AC 2. powerd_dbus_suspend --disable_dark_resume=false 3. fakebatt 5 4. fakebatt 4 Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9 Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-02-21mb/google/skyrim/var/markarth: Update Elan touchscreen power sequenceJohn Su
Based on product spec v1.4, update T3 timing from 180 ms to 150 ms. BRANCH=none BUG=b:262734395 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-17mb/google/skyrim/var/frostflow: Update Elan touchscreen power sequenceFrank Wu
Based on product spec v1.4, update T3 timing to 150 ms from 300 ms BRANCH=none BUG=b:269041202 TEST=emerge-skyrim coreboot chromeos-bootimage Then the Elan touchscreen works fine. Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-02-14mb/google/skyrim: Create whiterun variantIsaac Lee
Create the whiterun variant of the skyrim reference board by copying the winterhold files to a new directory named for the variant. BUG=b:265955979 BRANCH=None TEST=emerge-skyrim coreboot and boot up on Whiterun Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7 Signed-off-by: Isaac Lee <isaaclee@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-14mb/google/skyrim: Add support for and select USE_SELECTIVE_GOP_INITMatt DeVillier
Add a FMAP region to support caching GOP-driver-modified VBIOS tables. Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP. Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP. BUG=b:255812886 TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS in CBFS, cached VBIOS data is used when not booting in recovery or developer modes. Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-13mb/google/skyrim/var/frostflow: Update Package Power ParametersJohn Su
Follow thermal table to modify setting. "stapm_time_constant_s" = "200" to "275" BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7fe05fe1c17258a3323b8d04302212e76a388797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-11soc/amd/*: Add SOC_NAME in fw.cfg(s)Zheng Bao
2/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: I18f73462a3995038fe93750320dfc053fec969ba Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-10mb/google/skyrim: Disable keyboard resetMartin Roth
The keyboard reset is not being used on this board, so disable the functionality. BUG=None TEST=Check register values Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4a9f8f254dfefcb32a77f558f984bcdd6004d34b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72913 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10Revert "mb/google/skyrim: Update ASPM settings for the NVMe device"Martin Roth
This reverts commit 8e1bb93fb88bc9cc20aab33a1fe09fb4c0c652a0. Reason: Enabling L.2 breaks some devices on this bridge. Reverting until a workaround is found and additional testing is done. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9f721178244e7764e9b08e419db8a8c05ecc29a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72916 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>