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path: root/src/mainboard/google/rex/variants
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2024-03-30mb/google: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-02-26mb/google/rex/var/deku: replace IOEX with GPIOsEran Mitrani
IOEX was replaced with GPIOs, this CL makes the required changes BUG=b:325533052 TEST=Built FW image correctly. Change-Id: I09ebba336b179cb36c6801b47ee0be5ade08c257 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80570 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-26mb/google/rex/var/deku: Correct GPIO F19/F20 to not connectedEran Mitrani
GPP_F19 and GPP_F20 sre set incorrectly previously. Change them to not connected according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Change-Id: Ifb6da1f8696f44cb47be3d1de83c55e62b12a9e9 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80569 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-25mb/google/rex/var/deku: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage. TEST=Able to build and boot google/deku using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80664 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-25mb/google/rex/var/karis: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) | v ramstage (A19/1, A20/1) Ideally, we don't need SSD power sequencing at ramstage, but due to the fact that Karis has RO locked, any change in the bootblock won't be applicable for FSI'ed karis devices. Therefore, we're keeping the existing ramstage power sequencing flow as is TEST=Able to build and boot google/karis using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80663 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-25mb/google/rex/var/ovis: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage. TEST=Able to build and boot google/ovis using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-25mb/google/rex/var/rex0: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage. TEST=Able to build and boot google/rex0 using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-25mb/google/rex/var/screebo: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) | v ramstage (A19/1, A20/1) Ideally, we don't need SSD power sequencing at ramstage, but due to the fact that Screebo has RO locked, any change in the bootblock won't be applicable for FSI'ed screebo devices. Therefore, we're keeping the existing ramstage power sequencing flow as is. TEST=Able to build and boot google/screebo using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I0ee1fa4613178da8771c9e6b5ee871e50ea6324c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80640 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22mb/google/rex/variants/deku: Enable PCIe wifi deviceTony Huang
BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot built FW image correctly. Change-Id: I8db065e25e21406f1966d8020a3b926b3a62ae12 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-17mb/google/rex: Do not power on FPMCU in ramstagePatryk Duda
When 'reset_gpio' and 'enable_gpio' properties are defined in overridetree.cb, the kernel will power on the FPMCU. If the device was previously enabled the kernel will reset it. To avoid situation in which the FPMCU is powered on and reset later we leave the FPMCU powered off in coreboot and started by the kernel. This is exactly what other boards do (e.g. brya). TEST=Boot the board (e.g. karis) and make sure the FPMCU was booted once (e.g. examine FPMCU console logs) Change-Id: I5df8d9385be2621c02ccee2d36511a4e80ab87d1 Signed-off-by: Patryk Duda <patrykd@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13mb/google/rex: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id93cfea93edfefc8237b53214734531b811b36e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80202 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13mb/google/rex: Set display output type for eDP panelMatt DeVillier
Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: I8f390c58710c91bf77555f664e8f89f08ca59b30 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-03mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switchingTyler Wang
Follow reference design rex0, keep the GPIO settings of CNVi/PCIe. Only set GPP_F04,GPP_F05/GPP_S01,GPP_S02 to NC when WIFI_PCIE/WIFI_CNVI is selected. BUG=none TEST=Build and test on karis Change-Id: Id23a2cfe0639f2d423980db9badc16c1477434d1 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-03mb/google/rex/var/karis: Update fw_config KB_TYPE fieldTyler Wang
Update element "KB_TYPE_CA" for align fw_config. Only EC will reference KB_TYPE field in fw_config. This CL is just for align fw_config. BUG=none TEST=emerge coreboot pass Change-Id: Ied54f78dddd9dddca1272fc31c9502fc11c61dde Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2024-01-31mb/google/rex/variants/deku: correct GPIO E08 and E22 configurationEran Mitrani
GPP_E08 and GPP_E22 were set incorrectly previously. This CL corrects these settings according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I8e427350e1ee564f9d6566bdfe1f42c92c87a711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-30mb/google/rex/variants/deku: Add H58G66BK7BX067 to RAM ID tableTony Huang
Add RAM ID for H58G66BK7BX067 0 (0000) BUG=b:322528721 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: I31538988d1329d9e2f45d862eb0ae05c0d6a179e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-30mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblockTyler Wang
Check MTL EDS2, SOC_TCHSCR_RST(GPP_C01) default setting is NF1. Set SOC_TCHSCR_RST to output low in early_gpio_table. BUG=none TEST=Build and test on karis, touchscreen function works Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-30mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSDTyler Wang
Follow reference design rex0, toggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=none TEST=Build karis and try warm reboot from OS console. Check the DUT with WD SSD boots to OS again. Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80213 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26mb/google/rex/var/karis: Skip tcc_offset overrideSubrata Banik
This change eliminates the unnecessary override of the tcc_offset chip configuration to 10, as the default rex baseboard now handles this setting correctly. TEST=Successfully built and booted google/karis, confirming tcc_offset remains at 10. Change-Id: Ie40db1431fb0197ee360ad5656878e57f51c855b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-26mb/google/rex/var/screebo: Modify TCC_offset to 20Subrata Banik
Follow thermal team request, override tcc_offset to 20. TEST=Build and verified by thermal team using google/screebo. Change-Id: Idc76f9c0054f21f066b779e6404a1c175eb396a0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-25mb/google/rex/variants/deku: update USB-C port configurationTony Huang
This CL update setting according to schematic v0.4. BUG=b:320201111 BRANCH=firmware-rex-15709.B TEST=Built FW image correctly. Change-Id: Ia4570d26ee9fd175ed9099bd057cee3c30c95704 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80156 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-01-24*/mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth
Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24mb/google/oak to rex: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I85cda24aa7dec82d23e8a321dac03ec737f4c503 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80108 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/rex/var/rex: Set TCC to 100°CSumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for rex. BUG=b:270664854 TEST=Build, boot and test on rex with value under sysfs /sys/bus/pci/devices/0000:00:04.0/tcc_offset_degree_celsius Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79992 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Peter Ou <peter.ou@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-03mb/google/rex/var/screebo: Prevent camera LED blinking during bootJason Chen
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot, preventing privacy LED blink. BUG=b:317434358 TEST=none Change-Id: I43044e64c2c3a645ec0cad2ac903cc19ac89c9af Signed-off-by: Jason Chen <jason.z.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79803 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-01-02mb/google/rex/var/karis: Enhance CNVi and PCIe switchingTyler Wang
1. Set PCIe related GPIOs to NC if fw_config use "WIFI_CNVI". 2. Set CNVi related GPIOs to NC if fw_config use "WIFI_PCIE". 3. Remove "ALC5650_NO_AMP_I2S" case in fw_config_gpio_padbased_override(). bt_i2s_enable_pads should not relevant to audio codec/amp, and it is already enabled in "WIFI_CNVI" case. BUG=b:312099281 TEST=Build and test on karis Change-Id: Ib1a32f1a38ae33cf992b80a3408aa8e2fa3ddab0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79765 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-23mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control,the values before Sensor1 and Sensor2 were set too high. Modify the protection temperature to better meet DUT requirements. BUG=b:291217859 BRANCH=none TEST=emerge-rex coreboot Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-22mb/google/rex/var/karis: Adjust touchscreen power-on sequenceTyler Wang
According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high should over 5ms. And current measure result is 200us. Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet requirment. Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high: Power on --> 31.7 ms Resume --> 38.7 ms BUG=b:314245238 TEST=Measure the sequence Change-Id: I56e455a980b465f27794b30df058ec0944befc2e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-21mb/google/rex/var/karis: Add HDMI/eDP GPIOs to early GPIO listTyler Wang
Add HDMI GPIO configuration to early GPIO list to support VGA text o/p in Pre-RAM stage on HDMI. BUG=b:316982707 TEST=Erase MRC cache and reboot, SOL text display on HDMI/eDP Change-Id: Idb2af56baeb4d0ef9db5fc1c5dbcebecee6515e6 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79572 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-12-21mb/google/rex/var/screebo: Remove Camera EEPROM off timingWentao Qin
Since the camera sensor and camera eeprom share GPP_A12, remove the off timing to avoid issue of camera sensor loss, but this will increase system power by 5mW. (Before root cause, this is a short term workaround to unblock function test.) BUG=b:298126852 TEST=1. Run coldreboot/warmreboot check see if the camera sensor lost. 2. Run S0ix check to see if the camera function abnormal. Change-Id: I49b6ecbfbf3dddd6575bdaaf9c8fd0ee6c09af25 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79647 Reviewed-by: Jason Z Chen <jason.z.chen@intel.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2023-12-21mb/google/rex/var/screebo: Configure slew rate to 1/8 for GT domainKun Liu
set slew rate to 1/8 for GT domain. BUG=b:312405633 BRANCH=none TEST=Able to build and boot google/screebo Change-Id: Ib5cb07b7effc4a51c2119183010a03e026f639f8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
2023-12-21mb/google/{brya,brox,rex}: Update ec_sync wake capabilityMark Hasemeyer
Some of the boards use the EC_SYNC pin to wake the AP but do not advertise the pin as wake capable in the CREC _CRS resource. Relevant boards were determined through empirical testing and inspection of gpio configuration. Update the ACPI tables for rex, brya, and brox based boards to advertise their EC_SYNC pin as wake capable. BUG=b:243700486 TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined -Wake Aviko via keypress and verify chromeos-ec as wake source -Wake Screebo via lid open and verify chromeos-ec as wake source Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20mb/google/rex/variants/deku: correct GPIO configurationEran Mitrani
GPP_B02 and GPP_B03 were set incorrectly previously. This CL corrects these settings according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id62f15f7a77ac43c72cc6b2645816d6c87133a0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20mb/google/rex/var/karis: Add PANEL_PWRSEQ_EC_CONTROL in fw_configTyler Wang
Only EC will use field "PANEL_PWRSEQ_EC_CONTROL". Add this field in coreboot for align fw_config settings. BUG=b:314245238 TEST=emerge coreboot pass Change-Id: Icecb44a338ddc28027e362332c6a69cc9fd268d5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79570 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20mb/google/rex/var/karis: Update fw_config FAN fieldTyler Wang
After confirm with thermal, only EC will reference FAN field in fw_config. Update the settings for align fw_config. BUG=b:307822225 TEST=emerge coreboot pass Change-Id: Id7c4cdba29c5500c06d0f2293495650bb14b9e9c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79573 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-12-20mb/google/rex/var/screebo: Configure Acoustic noise mitigationSubrata Banik
Enable Acoustic noise mitigation for google/screebo and set slew rate to 1/8 for IA domain and ignore the slew rate for SA domain. BUG=b:312405633, TEST=Able to build and boot google/screebo. Before: [SPEW ] AcousticNoiseMitigation : 0x0 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x0 [SPEW ] SlowSlewRate for Index = 0 : 0x0 After: [SPEW ] AcousticNoiseMitigation : 0x1 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x1 [SPEW ] SlowSlewRate for Index = 0 : 0x2 Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-19mb/google/rex/var/screebo: Add delay 1ms after Main 3V3Kun Liu
when S0ix returns S0, PERST needs to delay until Main 3V3 is stable and then pull up BUG=b:313976507 TEST=emerge-rex coreboot,measurement waveform verify pass Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-18mb/google/rex/var/karis: Enable audio BT offloadTyler Wang
BUG=b:312099281 TEST=Build and boot to Karis. Verify the config from serial logs. w/o this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 0 [SPEW ] BT Interface = 1 ``` w/ this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 1 [SPEW ] BT Interface = 1 ``` Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-16mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectationSukumar Ghorai
The default EPP is set at 50%, which is deemed insufficiently aggressive for meeting the MTL performance expectations in balance_performance mode. # cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference balance_performance # iotools rdmsr 0 0x774 0x0000000080003f06 EPP=45% is giving the required performance in MTL. # iotools rdmsr 0 0x774 0x0000000073003d06 NOTE: Kernel changes are necessary to ensure that the EPP (Energy Performance Preference) configured in the BIOS is not overwritten: https://patchwork.kernel.org/patch/13461932 BUG=b:314275133 TEST=Build and boot. Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79386 Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14mb/google/rex/var/screebo: Change GPP_B14 from UP_20K to NONEKun Liu
Change GPP_B14 from UP_20K to NONE for compatible with DVT1 and DVT2 board BUG=b:272447747 TEST=enable usb OC2 function to ensure USBA work normal Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12mb/google/rex/var/screebo: Increase PL1 max value from 15W to 25WKun Liu
Adjust PL1 max value from 15W to 25W BUG=b:314263021 TEST=emerge-rex coreboot Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08mb/google/rex/var/screebo: set audio GPIO pins based on fw_configTerry Cheong
Enable BT offload when I2S option is selected for screebo. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/screebo. Fixes: https://review.coreboot.org/c/coreboot/+/77755 Change-Id: I7ebe8e28d35428ce2fb8129dc145fec9ac60f9da Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06mb/google/rex/variants/deku: Enable CNVi PCI deviceEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I41a64252f08304ffc66fd782e54720252064ca49 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/screebo: Override power limitsSubrata Banik
This patch allows variants to override the default baseboard PLx limits. Additionally, rearrange the include header files alphabetically. BUG=b:313667378 TEST=Able to boot google/screebo with modified power limits. Before: [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) After: [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-04mb/google/rex/variants/deku: Complete USB configurationEran Mitrani
+-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/variants/deku: Add basic DTTEran Mitrani
Add default Intel DPTF. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/deku: Enable LAN0, LAN1Eran Mitrani
google/deku is a Chromebox featuring two LAN ports. Add overridetree.cb entry to configure the LAN0 LAN1 devices. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14Subrata Banik
This patch adds the power limit configuration for MCH ID index 3 aka 0x7d14 DID which is identical to MCH ID 0x7d01 (index 1). TEST=Able to perform power limit configuration for google/ovis. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (19000, 28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79332 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-04mb/google/rex: Simplify power limit configuration usageSubrata Banik
This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE configurations, relying instead on the refactored power limit flow. This flow allows for seamless overrides by the baseboard and/or by the variant board, if necessary. Specifically, this patch: - Removes PL_PERFORMANCE and PL_BASELINE configuration options from mainboard.c in the google/rex directory. - Relies on the baseboard_devtree_update() function, which is implemented by the respective baseboard, to handle power limit configuration. - Leverages the variant_devtree_update() function, which is a __weak implementation, to allow overrides by the variant directory. This simplification improves code readability and maintainability while maintaining the flexibility to handle power limit configurations as needed. Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02mb/google/rex: Enhance power limit override mechanismSubrata Banik
This patch expands the power limit override capability to include variants directories, enabling them to modify power limit settings configured by the baseboard. Previously, only the baseboard could override power limit settings. For instance, while the google/rex baseboard sets the PL1 max power limit to 15W, the google/screebo variant couldn't override this value. This enhancement empowers variants directories to override baseboard- configured power limit settings, allowing for greater flexibility and control over power limits. BUG=b:313667378 TEST=Able to call into _weak implementation of `variant_devtree_update` unless there is one override. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-30mb/google/rex/variants/deku: Add GPIO configurationEran Mitrani
Based on Platform Mapping Document for Deku (go/cros-deku-mapping) from Nov 8, 2023 (Rev 0.4) BUG=b:305793886 TEST=WIP, not tested yet Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78960 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-29mb/google/rex/var/screebo: Change GPP_B14 from NC to NFKun Liu
Change GPP_B14 from NC to NF BUG=b:272447747 TEST=enable usb OC2 function to ensure USBA work normal Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-27mb/google/rex/var/screebo: Enable BT audio offload configKapil Porwal
Enable BT audio offload of ALC1019_ALC5682I_I2S based on fw_config. BUG=b:299510759 TEST=Build and boot to Screebo. Verify the config from serial logs. w/o this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 0 [SPEW ] BT Interface = 1 ``` w/ this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 1 [SPEW ] BT Interface = 1 ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I6c713752f3f0bf58b5ebd78b904e773fdbf16e06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77755 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-22mb/google/rex/var/karis: Set pen detect pin to NC for non-stylus skuTyler Wang
Set pen detect pin to NC base on fw_config. BUG=b:304680060 TEST=emerge-rex coreboot pass Change-Id: Icf9171fca49cfed1a05a67ae7fc8d62b7e9630c9 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79213 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-10mb/google/rex/var/screebo: Update DFP portzhourui
Update DFP port setting for retimer power GPIO BUG=b:302428013 BRANCH=none TEST=Retimer enumaration in NDA works. Change-Id: Idc1a728ec4cbb66e776c2700025db41d85801c60 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-09mb/google/rex/variants/deku: Add display configurationEran Mitrani
Enable DDI on ports 1 to 4 for Type-C DisplayPort. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I3acaff4a9306f2d058ce9542e8956ee0acba94cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78498 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/rex: split TOUCHSCREEN_I2C_SPI definitionYH Lin
As TOUCHSCREEN_I2C_SPI will be used for two different configurations, splitting it to TOUCHSCREEN_GSPI and TOUCHSCREEN_THC, and re-order the FW_CONFIG bits by moving VPU to different bit position. BUG=b:307774932 TEST=build and boot rex Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ied4d732ef7993e95edbb7eb281842b9392e72820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-07mb/google/rex/variants/deku: Add USB configurationEran Mitrani
+-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I743fd82f088a57e906b8b9d0fe2e012d9c5f9567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78497 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07mb/google/rex/variants/deku: Add SSD card configEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I167a02bf2219c6ef8e0093956a649305c8e8f76b Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-07mb/google/rex/variants/deku: Add I2C configEran Mitrani
Add I2C config based on Deku schematics. TPM is connected to I2C 4 BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I496e236531b2b59b320c77c36f542f4fa80a51a1 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78449 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07mb/google/rex/variants/deku: Add RAM id for MT62F2G32D4DS-026Eran Mitrani
Add RAM id for: MT62F2G32D4DS-026 WT:B (Micron) BUG=b:305793886 TEST=Run part_id_gen tool without any errors Change-Id: If2ed2bdcee44f6dbbda51a3ff484edaf3df4830d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-01mb/google/rex/var/rex0: Toggle NVMe PWR pin to reset SSDWonkyu Kim
During warm reboot, NVMe is not detected with non-serial image sometimes while there is no issue with serial image. This change toggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=b:260547988 BRANCH=None TEST= Build rex0 and try warm reboot from OS console. Check if the platform with Micron SSD boots to OS again without an issue. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I2f34e3f49e7fc388198ff85c8e119cb3f242a60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-01mb/google/rex: Avoid hang for pre-prod SoC by setting SAGV_POINTS_0_1_2Subrata Banik
Intel has identified an idle hang issue on pre-prod silicon that will not be fixed or root-caused. To avoid the issue, this commit sets SaGvWpMask to SAGV_POINTS_0_1_2 in the devicetree. Note: This change will affect system power. BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang on google/screebo. Change-Id: Id0b8db0076d983d336c3bec6d6c33614c69964d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78794 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31mb/google/rex/var/screebo: Disable FVMSubrata Banik
This patch disables FVM for IA and SA VRs as per the OEM requirement. BUG=b:307237761 TEST=Able to build and boot google/screebo. Change-Id: Icb0611331ac7090d11d646a5ad5201593a90aacb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31mb/google/rex/var/screebo: Set Baseline Power LimitSubrata Banik
This patch allows google/rex mainboard to choose between "Performance" (PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs). This is important for platform to meet balance between power and performance. The OEM design google/screebo selects baseline power limit to maintain the balance performance in lower power. BUG=b:307237761 TEST=Able to build and boot google/screebo. w/o this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 57 Watts [INFO ] CPU PL4 = 114 Watts w/ this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 40 Watts [INFO ] CPU PL4 = 84 Watts Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28mb/google/rex: add dptf settings for 2+4 SOC SKUKane Chen
This patches privides settings based on 2+8 15w. BUG=b:306543967 TEST=boot on rex with 2+4 SOC and power limit settings are overridden correctly in variant_update_cpu_power_limits Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28mb/google/rex/var/rex0: Configure EN_WWAN_PWR GPIO based on CBIJeremy Compostella
GPP_B17 (aka. EN_WWAN_PWR) should be kept low when the device does not have a WWAN module. TEST=Power consumption drops to 0 in S0iX Change-Id: I95150c20c98b037a47827a7b83e4373c6e9070e3 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78684 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28mb/google/{rex, ovis}: Introduce devicetree.cb for pre-prod SoCSubrata Banik
This patch introduces a dedicated devicetree.cb file for platforms built with pre-production SoC. This will help to keep the SoC configuration separate for platforms with ESx and QSx silicons. For example, the SaGv WP configuration is different between pre-production (aka ESx) and production (aka QSx) silicon. BUG=b:306267652 TEST=Able to build and boot google/rex4es. Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
2023-10-25mb/google/rex: Create deku variantEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku built without errors. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I332e404e82a7980bb8ed1fb084fe957f526f81d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78393 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-23mb/google/rex/var/karis: Modify TCC_offset to 10Tyler Wang
Follow thermal team request, modify tcc_offset from 20 to 10. BUG=b:306548525 TEST=Build and verified by thermal team Change-Id: I7537e103be4cd1196c934ca72dbd61e064aed371 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-10-23mb/google/rex: Use upstream driver properties for SX9324Ivy Jian
Use human readable properties as upstream driver support. BUG=b:297977526 TEST=Able to get sensor values changed w/wo a hand covering the device. before this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { Zero, Zero, Zero }, ... Package (0x02) { "semtech,ph23-resolution", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, .... after this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { One, 0x02, 0x02 }, ... Package (0x02) { " semtech,ph23-resolution", 0x0400 }, Package (0x02) { "semtech,startup-sensor", One }, Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78174 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
2023-10-20mb/google/rex/var/karis: Remove I2C2 "on" settingsTyler Wang
GPP_H04/GPP_H05 doesn't use for I2C usage, remove I2C2 "on" settings. BUG=b:294155897 TEST=Check ap firmware log, i2c2 is disabled Change-Id: I0124fd108fbbd87507d252e9caab4dfc16aceddb Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78339 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/google/rex: Set frequency and gears for SaGv pointsBora Guvendik
Update SaGv gears and frequency values as per recommendation from power and performance team. This change doesn't cause negative impact on firmware boot time performance. BUG=b:274137879 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ie8a81c05f25b1cdab1008d09c606d1debea6e6e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-20mb/google/rex/var/karis: Use 2 gpio for stylus detect/wakeTyler Wang
Use 2 gpio for stylus detect and wake function. GPP_E04 is the IRQ source, and GPP_E09 is the wake source. BUG=b:304680060 TEST=Build and test on karis, stylus detect function works Change-Id: I7a83326f76932c8e501e6369bb845fc7236291b4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78336 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/rex/var/karis: sync CBI FW_CONFIG definitionsYH Lin
Sync'ing Karis' FW_CONFIG definitions stored in CBI, ``` _FW_MASKS = struct( DB_USB = 0x00000003, # bit1~bit0 STYLUS = 0x00000004, # bit2 AMP = 0x00000038, # bit5~bit3 FAN = 0x000000C0, # bit7~bit6 MIPI_CAM = 0x00000300, # bit9 ~ bit8 FP_MCU = 0x00000C00, # bit11 ~ bit10 KB_TYPE = 0x00001000, # bit12 WIFI_TYPE = 0x00002000, # bit13 ) _FW_CONFIGS = struct( DB_USB_UNKNOWN = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 0), DB_USB4_ANX7452 = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 1), STYLUS_ABSENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 0), STYLUS_PRESENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 1), AUDIO_ALC5650 = hw_topo.make_fw_config(_FW_MASKS.AMP, 0), FP_MCU_ABSENT = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 0), FP_MCU_NUVOTON = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 1), FP_MCU_ELAN = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 2), WIFI_TYPE_CNVI = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 0), WIFI_TYPE_PCIE = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 1), MIPI_UF_CAM_HI556 = hw_topo.make_fw_config(_FW_MASKS.MIPI_CAM, 0), ) ``` BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I1e4965c009edc595f24c04ac82d81aa0e723bbf3 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78261 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-18mb/google/rex/var/karis: add hook for WiFi SAR tableYH Lin
WiFi SAR table for karis will be place into the CBFS later on and as a result adding the hook in coreboot to make use of the SAR table once the table is available. BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78260 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/rex/var/karis: Add FAN field in fw_configTyler Wang
Update default fan settings(FAN_SETTING_1) in FAN field. Bit 6-7, FAN, 0 --> FAN_SETTING_1 BUG=b:290689824, b:294155897 TEST=Dump ssdt table and check fan settings is existed Change-Id: Id69ec67202b5d769cd3a9a68344a6d8913ebd78b Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-16mb/google/rex/var/rex: Configure cpu power limits by battery statusJamie Ryu
When battery level is below critical level or battery is not present, cpus need to run with a power optimized configuration to avoid platform instabilities. This will check the current battery status and configure cpu power limits properly. BUG=b:296952944 TEST=Build rex0 and check cpu power limits are configured with a performance efficient configuration and the platform boots to OS if battery level is above the critical level. And check cpu power limits are configured with a power optimized configuration and boots to OS without an issue if battery is not present or battery level is at or below critical level. Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78322 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-13mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZEran Mitrani
BUG=NONE TEST=Tested on Rex, touch over SPI works properly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-13mb/google/rex/var/rex0: Update NVM configuration for WFCJamie Ryu
This updates NVM Configuration according to EEPROM BRCA016GWZ-W datasheet for rex World Facing Camera module - O9B13-NT01BA to enumerate Camera module properly. BUG=b:301226048 TEST=Build rex0 and check SSDT table is updated correctly. Check "cros-camera-tool modules list" lists up the modules properly. cros-camera-tool modules list: /sys/devices/pci0000:00/0000:00:15.0/i2c_designware.0/i2c-0/i2c-PRP0001:01/i2c-PRP0001:011/nvmem /sys/devices/pci0000:00/0000:00:19.1/i2c_designware.4/i2c-13/i2c-PRP0001:03/i2c-PRP0001:032/nvmem [ { "module_id": "KC6977", "sensor_id": "OV013b", "sysfs_name": "i2c-0/i2c-PRP0001:01" }, { "module_id": "CH3c6d", "sensor_id": "HN0556", "sysfs_name": "i2c-13/i2c-PRP0001:03" } ] Change-Id: I51bdf249549d3e03180e9d126a85e9dff91028db Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78211 Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-13Revert "mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang"Wentao Qin
This reverts commit 5c35d30ffc7382af46b62044a5cf5326b1e57708. Reason for revert: Here we need to confirm whether the issue in mtl-staging-MTL.3323.92 has been improved in the QS sample in the factory build. BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang. Change-Id: I4517bbbefe11d95623d7e16a5e4bba2dd6f408e1 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78320 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-12mb/google/rex/var/karis: Fix touchscreen HID to ELAN9004Tyler Wang
Confirmed with vendor, Elan touchscreen HID should set to "ELAN9004". Correct Elan touchscreen HID to "ELAN9004" for karis. BUG=b:294155897 TEST=Dump the SSDT on karis and check the HID had been modified. Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78266 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-11mb/google/rex/var/karis: Set touchscreen power/reset GPIOs correctlyTyler Wang
The tochscreen isn't powered on yet when the detection is done, it makes touchscren no function. Set touchscreen power and reset GPIOs correctly in romstage and ramstage to make the detect feature works. BUG=b:303130400 TEST=(1) emerge-rex coreboot (2) Test on karis, touchscreen function works Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78254 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-10mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control, as follows: 1.Cancel TCPU trip point and fine tune other protection temperature on the Critical policy table 2.Fine tune EC/Bios protection temperature BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-10mb/google/rex/var/rex0: update thermal settings to start fan earlierSumeet Pawnikar
Internal testing showed that CPU heatsink gets hot and temperature goes over 75C. In this situation, the fan does not even start to lower down CPU temperature. This is because of existing temperature thresholds of TSR0 and TSR1 sensors are set at 45C to start fan. With updated new settings based on tuning from thermal team, the fan starts early at 43C for TSR0 and TSR1 so the CPU temperature stays below 75C. BUG=b:302673874 TEST=Built and tested on google/rex board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I6580652d6165946e98ecf1b46ace3352cd34dcdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-07mb/google/{rex,ovis}: Disable package C-state auto demotionSukumar Ghorai
Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. BUG=b:303546334 TEST=Local build successfully & Boot to OS successfully - Also check platform enter PC8 state in local video playback - before this change: # iotools rdmsr 0 0xE2 -> 0x0000000060008008 - After # iotools rdmsr 0 0xE2 -> 0x0000000000008008 Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78250 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-04mb/google/rex: Configure ISH UART TX/RX as NCBernardo Perez Priego
This patch reverses ISH UART pin configuration to allow ISH to enter into suspend mode. This UART port is for debugging purposes. BUG=b:302612549 TEST=On Google/rex platform with ISH enabled, do suspend_stress_test This test must pass Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I8aba45420744a3990e1f9637c3b31ea2e0f78f87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78049 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-03mb/google/rex: Fix ISH I2C pad for suspendCliff Huang
During suspend, the ISH I2C transactions cannot go through because the GPIO pads remain the pervious value. The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus active and functional during suspend. BUG=b:302612549 TEST=on Google/rex platform with ISH enabled, do suspend_stress_test and check that no i2c failure. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/78179 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Li1 Feng <li1.feng@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/rex/var/ovis: Add DPTF configurationJakub Czapiga
Configure PL1 and PL2 are configured for powerformance. Based on values from Intel Meteor Lake UH Power Map document ID:640982 BUG=b:286834207 TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77623 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26mb/google/rex/var/rex0: Configure I2C5 timingIvy Jian
Configure I2C5 timing in devicetree to ensure I2C devices meet timing requirement. BUG=b:300177424 TEST=Build and check I2C devices timing meet spec. | | I2C5-Before | I2C5-After | |-------------|-------------|------------| | FSMB(KHz) | 445.400 | 343.638 | | TLOW(us) | 1.543 | 2.068 | | THIGH(us) | 0.475 | 0.604 | | THD:STA(us) | 0.603 | 0.711 | | TSU:STA(us) | 0.612 | 0.611 | | TSU:STO(us) | 0.605 | 0.611 | | TBUF(us) | >1.914 | >2.044 | Change-Id: I3bb678b66d55c6bfaff76e3e5500a2a3bc3a2c61 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78111 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/rex/var/rex0: Add entries for SAR Proximity SensorsSubrata Banik
This patch adds ACPI entries for SAR Proximity Sensors as below SAR1 Sensor: - SAR1_INT_L : GPP_E00 - I2C5 7-bit address 0x28 SAR2 Sensor:   - SAR2_INT_L : GPP_E08 - I2C 7-bit address 0x2c BUG=b:297977526 TEST=Able to build and boot google/rex. w/o this patch: Total 6 devices are listed below: > ls -lt /sys/bus/iio/devices/iio:device* /sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/ LNXSYBUS:00/PNP0A08:00/device:07/ /sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 w/ this patch: Total 8 devices are listed below: > ls -lt /sys/bus/iio/devices/iio:device* /sys/bus/iio/devices/iio:device6 -> ../../../devices/pci0000:00/ 0000:00:19.1/i2c_designware.4/i2c- /sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/ LNXSYBUS:00/PNP0A08:00/device:07/ /sys/bus/iio/devices/iio:device7 -> ../../../devices/pci0000:00/ 0000:00:19.1/i2c_designware.4/i2c- /sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 Change-Id: I0a518d58915f9f4dbe58a45c4dc5875abbfda135 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78045 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-09-21mb/google/rex/var/karis: Enable PIXA touchpadTyler Wang
Karis uses PIXA touchpad, update related settings. BUG=b:294155897 TEST=(1) emerge-rex coreboot (2) Test on karis, touchpad function works Change-Id: I26e3257485c4abe050de7a79c6d3b72dbd048710 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77517 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-20mb/google/rex/var/karis: Set VPU disable as defaultTyler Wang
BUG=b:299374763 TEST=emerge-rex coreboot Change-Id: I40fc768522e8679337c3b9f5497278e9f4639c3e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77888 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-19mb/google/rex/var/screebo: Change GPP_C06 to NCZhongtian Wu
GPP_C06 is the report pin of the touchpanel and has no actual function. Disable this pin to solve the leakage problem. BUG=b:298529441 BRANCH=none TEST=Test success by EE. Change-Id: I13f25788c0258639da4e277e7a15454a08d1599b Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77716 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-16Revert "mb/google/rex/var/screebo: Reduce TCC from 90°C to 80°C"Subrata Banik
This reverts commit 449c6d981c216e05d5238056f03c7794e43600ec. Reason for revert: (EVT board build does not exhibit shutdown followed by warm reboot) This commit reverts the workaround that limits the TCC activation temperature. The original issue that was reported (shutdown followed by warm reboot) was not seen in the EVT board build, so this change is likely unnecessary. Change-Id: I22adcdee6512e57ad0b6d531f2611e22a95c863e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-15mb/google/rex/var/karis: Disable stylus/FP module based on fw_configTyler Wang
There are going to be skus without stylus and fingerprint module. Disable stylus and fingerprint module based on fw_config. BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I047aae06c4a915d0392edc836757b882a261c178 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77647 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-15mb/google/rex/var/karis: Update fw_config settingsTyler Wang
Update fw_config settings for karis: | | | 0 --> STYLUS_ABSENT | | Bit 2 | STYLUS | 1 --> STYLUS_PRESENT | | | | | | Bit 3-5 | AUDIO | 0 --> ALC5650_NO_AMP_I2S | | | | | | Bit 8-9 | MIPI_CAM | 0 --> UF_CAM_HI556 | | | | | | | | 0 --> FP_ABSENT | | Bit 10-11 | FP_MCU | 1 --> FP_MCU_NUVOTON | | | | | | | | 0 --> WIFI_CNVI | | Bit 13 | WIFI_TYPE | 1 --> WIFI_PCIE | BUG=b:290689824 TEST=emerge-rex coreboot Change-Id: I1df30ad32d212a36b8a5bd7324f3eb8045b2795c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-15mb/google/rex: add support for UWBEran Mitrani
UWB on Rex will have 2 options to connect to the SoC: 1. Through GSPI1 (muxed with FP) 2. bit-bang over GPP This CL adds GSPI1 option. BB may be added later. BUG=b:263413448, b:263499898 TEST=UWB ranging works on Rex with this CL Change-Id: I93b3bcef84d775866df43d00c934f013e9f85c47 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76665 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07mb/google/rex/var/karis: Update MIPI User facing camera settingsTyler Wang
Update overridetree and GPIO settings for MIPI UFC due to updated schematic updates. BUG=b:298133153 TEST=emerge-rex coreboot Change-Id: I4c3197e3f15e0cb3fc640b1749d8681299981563 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77591 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-09-04mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hangWentao Qin
Setting SaGvWpMask to SAGV_POINTS_0_1_2 in dev tree can effectively avoid the idle hang issue, but it will affect the system power. (Before root cause, this is a short term workaround to unblock function test.) BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang. Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Change-Id: I0947815ab79b470d2ae922cffdd8250c60cf1afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/77520 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 05:07:25 +0000