diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-02-20 20:15:20 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-02-25 03:56:44 +0000 |
| commit | 4bbace87aa6c239cbfea7703daaa0135467109cc (patch) | |
| tree | 5b5af34c7381d46874004bdc0306747377b02533 /src/mainboard/google/rex/variants | |
| parent | f0277dbbe665e7af21868358b92bdfad617dcba2 (diff) | |
mb/google/rex/var/rex0: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/rex0 using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard/google/rex/variants')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/gpio.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 32388c4c83..4ccf327154 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -46,10 +46,6 @@ static const struct pad_config gpio_table[] = { /* GPP_A18 : [] ==> CAM_PSW_L */ PAD_CFG_GPI_INT_LOCK(GPP_A18, NONE, EDGE_BOTH, LOCK_CONFIG), - /* GPP_A19 : [] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), /* GPP_A21 : [] ==> WWAN_CONFIG2 */ PAD_CFG_GPI(GPP_A21, NONE, DEEP), @@ -376,10 +372,8 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* GPP_A19 : [] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_A19, 0, DEEP), /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 1, DEEP), + PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), @@ -417,22 +411,22 @@ static const struct pad_config early_gpio_table[] = { /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), -}; -static const struct pad_config romstage_gpio_table[] = { /* GPP_A19 : [] ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_A19, 1, DEEP), +}; +static const struct pad_config romstage_gpio_table[] = { /* GPP_B11 : [] ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_B11, 0, DEEP), - /* A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_C23 : [] ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPP_E07 : [] ==> WWAN_FCPO_L */ PAD_CFG_GPO(GPP_E07, 1, DEEP), /* GPP_D02 : [] ==> SD_PERST_L */ PAD_CFG_GPO(GPP_D02, 1, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) |