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path: root/src/mainboard/google/puff
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2024-07-13cfl/cml/whl mainboards: Drop superfluous cpu_cluster deviceFelix Singer
The cpu_cluster device is defined in the chipset devicetree. So drop it from the mainboards. Change-Id: I65bfeaf0b8771c123c0615531c2cc608b222949b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83440 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier
Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mb/google/puff: Hide LSPCON device from WindowsMatt DeVillier
Puff-based Chromeboxes use a LSPCON for HDMI 2.0 output, but no driver exists or is needed for Windows. Use the devicetree hidden keyword to set the ACPI status to hidden for these devices, to prevent unknown devices from being listed in Windows Device Manager. TEST=build/boot Win11 on google/wyvern, verify no unknown devices in Windows Device Manager for either LSPCON device. Change-Id: Ib646e01a337b8d7baf20a886c49a8cb64d6408f3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-02-08mb/google/puff/var/*: Clean up SerialIO/I2C config in overridetreeMatt DeVillier
Ensure that the SerialIoDevMode config and common_soc_config registers for each variant are programmed consistently with the devices' enabled status in that variant's overridetree; remove and disable extraneous devices as appropriate. TEST=build/boot several puff variants, verify all components working as expected, nothing missing from cbmem, lspci, etc. Change-Id: Ib9d0cf48e405be7c00c553646651fc6f28c4e3f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80164 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08mb/google/puff/var/*: Drop redundant device entries in overridetreeMatt DeVillier
Now that the puff baseboard uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default or the baseboard default, since they are pointless clutter. TEST=tested with rest of patch train Change-Id: Iada32111367fdc964d6126ee43e261c1feb123cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-08mb/google/puff: Delegate I2C device configuration to overridetreeMatt DeVillier
Don't enable the i2c controllers, since the variants will enable the ones they need individually in their overrridetrees. Disable gspi1 since all variants disable it in their overridetrees. TEST=tested with rest of patch train Change-Id: Ia9c67a8e05923a080e31d04721ecae4c810e82e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-08mb/google/puff: Drop devicetree entries identical to chipset.cbMatt DeVillier
Now that puff uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default, since they are pointless clutter. TEST=tested with rest of patch train Change-Id: I3a515f13df1252ed2b769a535da22a523c95c359 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80141 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08mb/google/puff: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I06a3acca0a72ff158a0143acc87d9479b2deb0d5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-24mb/google/oak to rex: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I85cda24aa7dec82d23e8a321dac03ec737f4c503 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80108 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21mb/google/puff/var/*: Set LAN device type back to pciMatt DeVillier
This mostly reverts commit 6c705e766f7f ("mb/google/puff/var/*: Set LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed correctly. Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-03mb/google/puff/var/*: Set LAN/WLAN device type to genericMatt DeVillier
Change the LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices function correctly under Windows and Linux. Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-25devicetrees: Remove trailing backslash from multiline valuesFelix Singer
It's not needed to put a backslash at the end of a line for quoted multiline values. Thus, remove it. Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/puff: Add VBT for Genesis variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware genesis_13324.283.0 TEST=build genesis with FSP GOP display init Change-Id: If836b214da1350111d7b7d1f24865199f814c521 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-09-22mb/google/puff: Add VBT for Ambassador variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware ambassador_13324.283.0 TEST=build ambassador with FSP GOP display init. Change-Id: I5c47700c5abe7d96112702d48a2b749f1784a494 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78032 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-22mb/google/puff: Set early GPIOs to enable bootblock consoleMatt DeVillier
Without the PCH UART GPIOs set early, there is no serial console output until ramstage. Add them to the early GPIOs for all puff variants. TEST=build/boot google/puff (wyvern) with serial console enabled, verify console output starts in bootblock. Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06google/puff: Enable ASPM of RTL8111HAlexis Savery
With kernel 5.15, puff hangs during power idle tests because the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in devicetree for RTL8111H to enable ASPM L1.2. BUG=b:268859220, b:279618219 TEST=emerge and run power.Idle Change-Id: I129dfd79e8112191453be513b2e3a260429b3030 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06google/puff: remove workaround that toggled the #ISOLATE pinAlexis Savery
A workaround was added for puff to assert/deassert the #ISOLATE pin during suspend/resume to resolve the situation where the realtek ethernet device cannot enter L1.2 mode when its ASPM is disabled. The realtek driver has since been fixed and ASPM of realtek devices have been enabled on kernel 5.10 and 5.15 and this original workaround is now causing suspend/resume errors on kernel 5.15: r8169 0000:01:00.0: Unable to change power state from D3cold to D0, device inaccessible Puff devices were originally shipped with kernel 4.19, and applying this change to the firmware on a device running 4.19 causes suspend/resume failures, basically reversing the problem. We are upreving the puff kernel to 5.15 so we need this patch, but since it is incompatible with 4.19 we will have to take that into consideration when pushing new firmware and potentially will need to backport the necessary fixes to 4.19. BUG=b:268859220 TEST=suspend_stress_test -c 500 on wyvern Change-Id: I5eead2d70cd9528b3ca3fadd11f98c0330601324 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77378 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-05-04mb/google/puff: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on wyvern variant, verify headphone output and microphone functional under Windows using coolstar's SOF drivers. Change-Id: I421c070eac321c2fc160b8f26868bcb1ec13001e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74815 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-17Makefiles: Drop redundant VARIANT_DIR definitionsKyösti Mälkki
Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-18mainboard/google: Remove ACPI ALS deviceGwendal Grignou
Remove the ACPI ALS device from the EC configuration for newer devices, because some do not have light sensors, and those who do have their ALS presented through the new EC sensor interface already. Inspired from commit ("f13e2501525f ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device") BUG=b:253967865 BRANCH=none TEST=Boot a device and ensure that 'acpi-als' device is not present in /sys/bus/iio/devices. Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22mb/google/hatch: split up hatch and puff baseboardsMatt DeVillier
The hatch and puff baseboards have diverged enough to where it makes more sense to split them into separate boards. Copy the mb/google/hatch directory into a new dir 'puff' and strip out all boards and items related to the hatch baseboard. Remove all puff-related items from the original hatch directory. Clean up and alphabetize Kconfig selections. Test: build and boot akemi hatch variant and wyvern puff variant. Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 14:32:37 +0000