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path: root/src/mainboard/google/poppy
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2018-01-12mb/google/poppy/variants/nami: Fix DA7219 IRQ issueKaiyen Chang
Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to meet the requirement of DA7219 IRQ pin. BUG=b:70646770 BRANCH=none TEST=Use aplay and arecord to verify headphone function. Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23160 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-12mb/google/poppy: Remove digitizer reset control from ACPIFurquan Shaikh
Digitizer power is not controlled by SoC. Also, since the digitizer uses I2C-HID driver in Linux kernel, the device is put into sleep anytime system is suspended. Thus, there is no need to control the reset gpio using ACPI power resource. TEST=Verified that digitizer device is properly detected on boot-up and after suspend/resume. Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/google/poppy/variants/nautilus: enable digitizer pen deviceSeunghwan Kim
- Add pen device property into devicetree.cb. - Set GPP_C9 to 0 as default. BUG=none BRANCH=master TEST=emerge-nautilus coreboot and check pen device operation Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f Reviewed-on: https://review.coreboot.org/23010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-09mb/google/poppy: Add internal pull-up on pen eject signalFurquan Shaikh
Since the current hardware revision does not have external pull on the pen eject signal, this change adds internal pull-up on it. Change-Id: I426d9833d7efbd8735b6f2b4896d1012b62cb4b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-02mb/google/poppy/variants/nami: Add empty_ddr4.spd.hex for DDR4Kane Chen
The spd size of DDR4 is 512, but the size empty.spd.hex is 256. With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data loads spd data incorrectly due to the offset is wrong. Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/google/poppy/variants/nautilus: Change USB2 phy settingsh.kim
In order to pass USB2 eye diagram, some USB2 port PHY registers needs to be changed. Port1 (Type-A): USB2_PORT_SHORT Port2 (BT): USB2_PORT_SHORT Port6 (H1): USB2_PORT_SHORT Port7 (Camera): USB2_PORT_SHORT BUG=none BRANCH=master TEST=emerge-nautilus coreboot and do eye-diagram test Signed-off-by: sh.kim <sh_.kim@samsung.com> Change-Id: I174e5bf96a53bb210481fb88298d5341f6c11dec Reviewed-on: https://review.coreboot.org/22686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/google/poppy/variants/nami: Add SPD files for namiFurquan Shaikh
This change adds SPD files for memory IDs 1-4 on nami. BUG=b:70182907 Change-Id: Ic43f944c0cde18244fe4c4d21314b831d048a3a2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20mb/google/poppy: Enable speaker and codec for namiGaggery Tsai
Nami uses MAX98357A speaker amplifier and DA7219 codec. This patch adds max98357a and da7219 under I2C #3 in devicetree and adds SPK DMIC nhlt support for 4CH DMIC. BUG=b:70646770 TEST=emerge-nami coreboot Change-Id: Iecf4059f8ea3d5e34f33f0be227897a8cca636fa Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-19mb/google/poppy: Configure WWAN gpiosFurquan Shaikh
BUG=b:70773281 Change-Id: If9b575568cabcbee03ad190b69d9c033890f7fa6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22927 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure GPP_B0 for WLAN wakeFurquan Shaikh
As per the latest schematics, this change configures GPP_B0 for WLAN wake and uses corresponding gpe bit in ACPI node for WLAN. This hasn't been tested yet. BUG=b:70775494 Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22928 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure pen reset and eject linesFurquan Shaikh
This change configures the GPIOs for pen reset and eject lines and exports required properties using ACPI table. BUG=b:70773138 Change-Id: I52f6c3dced54259cde8ee6753275622622e15954 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 1Furquan Shaikh
Similar to other KBL projects, this change enables AER and LTR for root port 1 on poppy. BUG=b:65570878 Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_B8 for WLAN_PE_RSTFurquan Shaikh
BUG=b:62726961 Change-Id: I5a88e67d5a22f8a39427c95821ffee4f2fd717fa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nami: Fix SATA configs againFurquan Shaikh
This change really fixes the SataMode to select non-RAID mode and enables SATA which was incorrectly disabled in a71276b (mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree). BUG=b:70160119 Change-Id: Ied6adabdc1d2458972bde628616a198cd41f9f3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_F3 as NCFurquan Shaikh
GPP_F3 is not connected on poppy or any of its variants. This change configures GPP_F3 as NC on poppy and all the variants. BUG=b:70160119 Change-Id: I303276ab9546d56c846755fa3a6142978f6b8c92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nami: Fix GPIO configuration for DEVSLPFurquan Shaikh
Nami uses DEVSLP1 and not DEVSLP0. This change updates the GPIO configuration for DEVSLP to match the latest version of schematics. BUG=b:70160119 Change-Id: Ifa181322011a4b8947ecd0fa44dcf790b0d8f657 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-17mb/google/poppy/variants/nami: Fix SataMode configuration in devicetreeFurquan Shaikh
Similar to Fizz, SataMode on nami should be set to AHCI. This change fixes the configuration error done in 903472c (mb/google/poppy/variants/nami: Add support for nami board). BUG=b:70160119 Change-Id: Ia88b56ae6bd9121f8447f7c1a2f5a10990fb8ed5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22845 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-17mb/google/poppy/variants/nami: Fix GPIO config for PCH_SPK_ENFurquan Shaikh
PCH_SPK_EN uses GPP_A23 and not GPP_A22. This change fixes the gpio configuration error in the initial change 903472c (mb/google/poppy/variants/nami: Add support for nami board). BUG=b:70160119 Change-Id: I90d9c009369c53cfec47fe77356e181d5ecf7ad5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22844 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-13mb/google/poppy/variants/nami: Disable native SD card controllerFurquan Shaikh
This change selects Kconfig option to disable native SD card controller in ACPI tables, since it is not used on nami. BUG=b:70160119 Change-Id: I6180c2b342c69e6a7c357f10b6297d67ea0211d7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-12mb/google/poppy/variants/nami: Implement variant_memory_paramsFurquan Shaikh
This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11mb/google/poppy/variants/soraka: Tune I2C5 paramsFurquan Shaikh
This change updates scl_lcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:65062416 TEST=Verified that I2C5 frequency is between 389-396kHz. Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11google/nautilus: Add Maxim98357a supportNaveen Manohar
Adds Maxim98357a support for Nautilus using the generic driver in drivers/generic/max98357 BUG=b:68686020 TEST=With entire merged audio should be enabled on max98357 speaker codec. Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11mb/google/poppy/variants/nautilus: add SPK DMIC nhlt supportNaveen Manohar
Nautilus board uses max989357a speaker codec and 4CH DMIC. Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on Speaker and captures on 4CH DMIC Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07mb/google/poppy/variants/nami: Add support for nami boardFurquan Shaikh
This change adds variant nami derived from baseboard poppy. BUG=b:70160119 Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mb/google/poppy: Add support for DDR4 memoryFurquan Shaikh
This change updates memory SPD handling code in baseboard poppy to allow variants to define either LPDDR3 or DDR4 memory types. In addition to that, it also updates the function to print SPD info considering offsets that might be different across the two memory types. BUG=b:70188937 Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mb/google/poppy/variants/nautilus: Fix memory paramsFurquan Shaikh
Until now, nautilus was using the DQ-DQS mappings provided by the baseboard. However, based on schematics, these values are not correct. This change adds DQ-DQS mapping tables for nautilus. BUG=b:70188533 Change-Id: Ife6ba19b8fe8873ab8cca977ca8f34a4d86e8e6e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22706 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: shkim <sh_.kim@samsung.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/google/poppy: Remove variant_cros_gpios from variantsFurquan Shaikh
Variants nautilus and soraka currently provide the exact same definition for variant_cros_gpios as provided by the baseboard. This change removes the function defintions from variants so that the weak definition in baseboard can be used. Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22705 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/google/poppy: Add config option for camera ACPI supportFurquan Shaikh
This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow variants to define ACPI tables for camera support. It also prevents boards that do not need this from unnecessarily providing dummy files for camera ACPI support. Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_*Furquan Shaikh
Change the prefix for TPM options from POPPY_USE_* to VARIANT_HAS_*. This makes it clear that these are variant specific options. Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Introduce VARIANT_SPECIFIC_OPTIONS_*Furquan Shaikh
In order to allow variants to select different Kconfig options, this change adds VARIANT_SPECIFIC_OPTIONS_${VARIANT_NAME} which can be selected by each variant in Kcnonfig.name. Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Remove dynamic disabling of TPMFurquan Shaikh
This change removes the dynamic disabling of TPM based on config options. Poppy and its variants will have only one type of TPM supported and so there is no need to update it dynamically. Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22704 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06mb/google/poppy/variants/soraka: Disable SPI TPMFurquan Shaikh
Soraka is no longer using SPI TPM. This change disables GSPI0 in device tree and updates gpio config accordingly. Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Disable SPI TPMFurquan Shaikh
Mainboard poppy is no longer using SPI TPM. This change disables GSPI0 in device tree and udpates gpio configuration accordingly. Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-05mb/google/poppy,nautilus,soraka: Disable PD on AC_PRESENT in deep SxFurquan Shaikh
This change updates device tree deep_sx_config to disable internal pull-down on AC_PRESENT. BUG=b:69983729 Change-Id: I041900a5262f8fd920856f126185329242a0639a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-30mb/google/poppy/variants/nautilus: Disable DPTFFurquan Shaikh
This change disables DPTF until the support is properly added in dptf.asl Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-30mb/google/poppy/variants/soraka: Set PCH thermal trip point to 75 degreeCSubrata Banik
PMC logic shuts down the thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in S0ix is enabled. BUG=b:69110373 BRANCH=none TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)] value is 0xFA. Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-30mb/google/nautilus: add synaptics touch screen supportChris Wang
Add synaptics touchscreen in the device tree so that the correct ACPI device is created. BUG=b:66462881 BRANCH=master TEST=compiled/verify the touchscreen works Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-29mb/google/poppy/variants/nautilus: Disable camera devicesFurquan Shaikh
This change disables camera devices until camera support is properly added for nautilus. Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29mb/google/poppy: Add variant support for camera aslFurquan Shaikh
This change adds infrastructure to allow variants to define their own camera.asl file. - Poppy and soraka use the one provided by baseboard. - Dummy file is added for nautilus since it does not have camera support enabled yet. TEST=Verified that DSDT table remains the same with and without this change. Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28mb/google/poppy/variants/nautilus: set I2C speed to 400KHzChris Wang
Add "speed_config" for each I2C port configuration to set speed to 400KHz. BRANCH=master BUG=none TEST=compiled/verified Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settingsChris Wang
Change IA/GT/SA slow slew rate settings. System's audible noise will be reduced with them. - Slow slew rate for IA/GT/SA : fast/16 - Fast PKG C-state ramp for IA/GT/SA: disabled BRANCH=master BUG=none TEST=compiled/verified Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-28mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_tableDivya Chellap
On shutdown, Soraka enters Deep S5 and not S5 state. Setting pad reset config of a gpio to RSMRST will not preserve the gpio config across deepSx and the gpio should be configured again. The WLAN_PE_RST signal should be brought up early in the bootflow for giving the device enough time to initialized before PCIE init in FSP-S. Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in early pad configuration in bootblock also. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6 Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-28mb/google/poppy/variants/nautilus: correct the SIO_EC_ENABLE_P2SK typoChris Wang
correct the typo from SIO_EC_ENABLE_P2SK to SIO_EC_ENABLE_PS2K. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Iaded458e202bc975c73cd295f7b363e2c9bfa861 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28mb/google/poppy/variants/nautilus: remove ALS for nautilusChris Wang
nautilus doesn't support ALS. remove the definition from ec.h. BRANCH=master BUG=b:66462881 TEST=compiled/boot to ChromeOS. Change-Id: Ib357328799015f78b18cd260db221e524e98cef7 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09mb/google/{poppy,nautilus,soraka}: Disable deep S3Furquan Shaikh
Poppy and variants won't be using deep S3. This change disables deep S3 option in devicetree. BUG=b:69053636 Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22378 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07mb/google/poppy/variants/nautilus: Enable Dialog DA7219 supportNaveen Manohar
Enable Dialog DA7219 codec i2c device and add required SSDT parameters BUG=b:68686020 TEST=With req'd driver support in kernel v4.4 verify audio on headset Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com> Reviewed-on: https://review.coreboot.org/22264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07mb/google/poppy/variants/nautilus: add nhlt supportNaveen Manohar
Nautilus board uses Dialog da7219 headset codec, Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. Removes unwanted DMIC blob pick for nautilus BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on headset and recording on headset mic Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22325 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-03soraka: update pad reset config of WLAN_PE_RST to RSMRSTDivya Chellap
In skylake based platforms, setting GPIO pad reset config to DEEP will reset the gpio configuration across warm reset, set it to RSMRST to preserve the configuration across warm resets. Also, moving the configuration from early to late as appropriate. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03google/nautilus: enable elan touchpad supportChris Wang
add elan touchpad in devicetree. BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I30e6797ef06351690ff0b5c78ea76918547167a7 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03google/nautilus: Update GPIO tableChris Wang
Update GPIO settings to meet nautilus's schematic design. BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I11930df62130431764702371a3ba84949a65ba30 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-03google/nautilus: add spd data by ram idChris Wang
update with nautilus memory spds. RAM_ID = 0 => K4E8E324EB-EGCF RAM_ID = 1 => K4E6E304EB-EGCF RAM_ID = 2 => K4EBE304EB-EGCG BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-10-19mb/google/poppy: Log EC events during S0ix resumeFurquan Shaikh
This change adds support for logging EC events during S0ix resume. BUG=b:67874513 TEST=Verified that EC events are correctly logged during S0ix resume: 284 | 2017-10-16 20:45:12 | S0ix Enter 285 | 2017-10-16 20:45:16 | S0ix Exit 286 | 2017-10-16 20:45:16 | Wake Source | Power Button | 0 287 | 2017-10-16 20:45:16 | EC Event | Power Button 288 | 2017-10-16 20:45:35 | S0ix Enter 289 | 2017-10-16 20:45:40 | S0ix Exit 290 | 2017-10-16 20:45:40 | Wake Source | GPIO | 112 291 | 2017-10-16 20:45:40 | EC Event | Lid Open 292 | 2017-10-16 20:50:51 | S0ix Enter 293 | 2017-10-16 20:50:59 | S0ix Exit 294 | 2017-10-16 20:50:59 | Wake Source | GPIO | 112 295 | 2017-10-16 20:50:59 | EC Event | Mode change Change-Id: I9f6dcb8852d94ebf90bb5b63a17fde524d58d49f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-10mb/google/poppy/variants/nautilus: add nautilus boardChris Wang
Create Nautilus board which derives from Poppy, a KBL reference board. BRANCH=master BUG=b:66462881 TEST=Build (as initial setup) Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-09skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPIFurquan Shaikh
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all skylake boards to use common gpio driver. Common gpio code defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This resulted in Linux kernel failing to configure all GPIO IRQs since the ownership was not set correctly. (Observed error in dmesg: "genirq: Setting trigger mode 3 for irq 201 failed (intel_gpio_irq_type+0x0/0x110)") This change fixes the above issue by replacing all uses of PAD_CFG_GPI in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER. BUG=b:67507004 TEST=Verified on soraka that the genirq error is no longer observed in dmesg. Also, cat /proc/interrupts has the interrupts configured correctly. Change-Id: I7dab302f372e56864432100a56462b92d43060ee Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-08mb/google/poppy/variants/soraka: Add 10ms reset delay for WCOM deviceFurquan Shaikh
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time) removed the delay after taking device out of reset since it seemed unnecessary in system resume case (because there is enough time after taking device out of reset and before communication with device starts). However, without the delay, kernel driver runs into issue while talking to the device during boot-up and runtime suspend/resume. (Observed this error in dmesg: "i2c_hid i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms delay after taking device out of reset. Verified on multiple Soraka system that with 10ms delay, kernel driver does not run into any issue talking to the WCOM device during boot-up, runtime suspend/resume and system suspend/resume. BUG=b:65358919 TEST=No more errors talking to WCOM device in kernel dmesg. Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajat Jain <rajatja@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-08ec/google/chromeec: Add library function google_chromeec_events_initFurquan Shaikh
mainboard_ec_init implemented by all x86-based mainboards using chromeec performed similar tasks for initializing and recording ec events. Instead of duplicating this code across multiple boards, provide a library function google_chromeec_events_init that can be called by mainboard with appropriate inputs to perform the required actions. This change also adds a new structure google_chromeec_event_info to allow mainboards to provide information required by the library function to handle different event masks. Also, google_chromeec_log_device_events and google_chromeec_log_events no longer need to be exported. Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-03mainboard/google/soraka: Reduce Wacom resume timeRajneesh Bhardwaj
Currently the WCOMCOHO registers a reset delay of 110ms to execute their _ON_ asl power on method. This seems to be correct as per WACOM product design specifications but it introduces an unwanted delay in overall system resume time. This delay should be removed from ACPI critical path since the entire kernel resume gets blocked on this sleep call unless this is over. In the kernel I2C communication with WACOM driver starts with the resume callbacks of I2C HID driver which gets triggered after display is completely resumed. The display resume process takes at least 230ms so it's safe to reduce the delay from coreboot and unblock the critical ACPI path. BUG=b:65358919 BRANCH=None TEST=manual testing on Soraka board to ensure that touchscreen works at boot and after suspend/resume. Also verify that the overall S3 resume time is reduced by 110ms. Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/21692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-27mb/google/poppy: Modify HID and add device tree support for VCM deviceV Sowmya
Modify the HID to align with ACPI spec. Add the DSD object for the device tree support in kernel which will probe the DW9714 device based on the HID. BUG=b:65423422 CQ-DEPEND=CL:654383 BRANCH=none TEST=Build and boot soraka. Verified that the VCM device probe is successful. Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-26mb/google/*: Use newly added Chrome EC boardid functionFurquan Shaikh
Instead of duplicating code across multiple mainboards, use newly added helper function to read boardid from Chrome EC. Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26soraka: Ensure I2C5 frequency is less than 400kHzFurquan Shaikh
Update I2C5 bus parameters to obtain clock frequency <400kHz. BUG=b:65062416 TEST=Verified using an oscilloscope that I2C5 bus frequency in factory is ~397kHz. Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-21mb/google/{poppy,soraka}: Enable LTR for Root portRizwan Qureshi
Enable LTR for Root port 0, where wifi card is connected. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-16mb/google/poppy: Add lens_focus property for OV13858 camera moduleV Sowmya
Add lens_focus property with reference to VCM device for OV13858 camera module to register the corresponding v4l2 sub-device asynchronously. BUG=b:64133998 BRANCH=none TEST=Build and boot soraka. Dump DSDT and verified that it has the required entries and verified the camera functionality. Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21512 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15mb/google/poppy: enable AER for PCIe root port 0Rizwan Qureshi
Enable PCIe Advanced Error Reporting for PCIe root port 0. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21425 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13mb/google/soraka: Update DPTF parametersWisley Chen
Cloned from baseboard/dptf.asl and update the parameters for soraka. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU: passive point:85, critial point:100 TSR0: passive point:55, critial point:65 TSR1: passive point:58, critial point:70 TSR2: passive point:60, critial point:75 TSR3: passive point:60, critial point:75 2. Set PL1 Max to 7W, and PL1 Min 4.5W 3. Change sampling period of thermal relationship table (TRT) setting CPU: 5 seconds TSR0: 30 seconds TSR1: 30 seconds TSR2: 8 seconds TSR3: 8 Seconds BUG=b:65467566 TEST=build, boot on soraka, and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590 Reviewed-on: https://review.coreboot.org/21453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13mb/google/soraka: Fine-tune USB 2.0 port4Wisley Chen
Fine tune usb 2.0 strength for port 4 to pass eye diagram. BUG=b:65306272 TEST=build on soraka, measure usb2.0 eye diagram, and result is pass. Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06mb/google/{poppy,soraka,eve}: Add imon and vmon params for Max98927 codecHarsha Priya
This patch adds imon and vmon slot numbers for Maxim 98927 driver. These values are used to confiure IV feedback for audio playback on speakers. BUG=b:36724448 TEST=After boot, the register dump for Max98927 codecs should have imon and vmon slots numbers set in 0x1e register. Change-Id: I4382da4f984507d147751c168e8177b58c88a70f Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06mb/google/soraka: enable AER for PCIe root port 0Rizwan Qureshi
Enable PCIe Advanced Error Reporting for PCIe root port 0. Change-Id: I76742801e84449d0910ddadf31d39597df3263b9 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-05mb/google/soraka: Camera PMIC run time power controlNaresh G Solanki
Currently PMIC (tps68470) is in active state even when cameras are not in use. PMIC is put into SLEEP mode only when entering S3 via smihandler. With this change PMIC will be put into SLEEP mode as soon as sensors & VCM voltage outputs are turned off. This will allow run time power saving when camera is not in use. PMIC will be reset in first boot & across S3 & S0ix cycles. Also, remove the smi handler for PMIC power management & handle it as part of sensor and VCM ACPI PowerResource. BUG=b:63903239 TEST= Build for Soraka. Check Camera probe, Capture image across S3 & S0ix cycles. Also checked the following & found no regression: 1. Typical camera use cases 2. Stability tests related to camera 3. Reliability tests related to camera 4. PnP tests related to camera 5. Latency related tests with camera Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-02mainboard/google/soraka: Remove wacom digitizerWisley Chen
We have no wacom digitizer on I2C#3, so remove it. TEST=build and boot on soraka. Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21309 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-30mainboard/google/soraka: Add stop gpio control to touchscreen deviceFurquan Shaikh
BUG=b:64987428 TEST=Verified that touchscreen works on boot-up and after suspend/resume. No power leakage via stop gpio in suspended state. Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-30mainboard/google/soraka: Remove Atmel TouchscreenFurquan Shaikh
We no longer use this touchscreen device, so get rid of it. BUG=b:64987428 Change-Id: I67af787d231317a80998fb483eed5674de19aeb4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-29mainboard/google/soraka: Tune I2C params (hcnt, lcnt, hold time)Furquan Shaikh
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 393 - 397 I2C1: 393 - 400 I2C2: 392 - 400 I2C4: 392 - 400 I2C5: 392 - 400 Change-Id: I3e12c75eb7e82a83aa6a6bcfcc11c12f83f2d3d4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-28mainboard/google/poppy: Tune I2C params (hcnt, lcnt, hold time)Furquan Shaikh
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 375 - 400 I2C1: 377 - 400 I2C2: 377 - 400 I2C4: 375 - 397 I2C5: 375 - 397 Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21mainboard/google/poppy: Update VR config settingsFurquan Shaikh
Update Psi2Threshold, IccMax, ACLoadline and DCLoadline VR config settings to match that of soraka. BUG=b:62063434 BRANCH=None TEST=Build and boot poppy. Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21105 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-21mainboard/google/poppy: Remove MPS IMPV8 workaroundFurquan Shaikh
Poppy uses MPS2949 IMVP8 controller and does not need the VR workaround similar to Eve. Change-Id: If6fb1890e024e1488d278bbe0a71a1a63ee321af Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21104 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-17mainboard/google/poppy: Add ACPI objects for NVMEM device GT24C16S and CAT24C16V Sowmya
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16 are the industrial standard electrically erasable programmable read only memory (EEPROM's) and this patch adds ACPI objects and power resources for NVMEM device. Update DOVD method to set sensor IO LDO voltage and remove repetitive code from OVFI, VCMP and NVMP power resources. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Read the NVMEM content via sysfs interface. Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-11mb/google/poppy: Update PL2 settingsSumeet Pawnikar
Update PL2 override setting to 15W as per KBL Power Arch Guide. Change-Id: I4a6f875f8c3bdb012d6ff97c1429f32db5210893 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/20943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04mainboard/google/poppy: Decrease link-frequencies for OV13858 and OV5670V Sowmya
Decrease the link-frequencies as recommended by Omnivision for OV13858 and OV5670 camera sensors. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2017-08-04mainboard/google/soraka: Configure GPP_B8 in bootblockFurquan Shaikh
GPP_B8 acts as input to the inverter whose output controls PERST# signal to wifi module. Out of reset, GPP_B8 is configured as input by default. Since there is no external pull-down on it, this line is floating and results in PERST# being asserted until ramstage where the GPIO was originally configured. Because of this the wifi chip is not ready during the PCIe initialization step. Move the configuration of GPP_B8 to bootblock so that wifi device is taken out of reset as early as possible. BUG=b:64181150,b:62726961 TEST=Verified with warm reboot and suspend-resume stress test that wifi is still functional. Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04mainboard/google/soraka: Add gpio.c to bootblockFurquan Shaikh
Add gpio.c to bootblock so that the variant early_gpio_table can be used for configuration in bootblock. BUG=b:64181150,b:62726961 Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-28mb/google/soraka: configure GPP_B8 to control WLAN_PE_RSTRizwan Qureshi
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8. Configure GPP_B8 to drive low. TEST=Wifi card is detected and connect to an AP. Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/20804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27mainboard/google/poppy: Configure GPIO.1 and GPIO.2 for daisy chain modeV Sowmya
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively for TPS68470 PMIC in daisy chain mode. * GPIO.1: Sensor SDA in daisy chain mode. * GPIO.2: Sensor SCL in daisy chain mode. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-24mainboard/google/soraka: pull high TOUCHSCREEN_STOP_L pinWisley Chen
After updating to Wacom Firmware version 501, touchscreen can't work. Wacom FW (ver. 501) enables STOP function. STOP Pin: High: Normal Operation Low: Stop Scanning So pull TOUCHSCREEN_STOP_L high BUG=b:37007801, b:37265219 BRANCH=none TEST=manual testing on Soraka board and touchscreen works at boot and after suspend/resume. Change-Id: I8a2bdce1554fd99dea30cf91fa48d0529f40b7b0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/20664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-23mainboard/google/{poppy,soraka}: Enable S0ixRajat Jain
Enable S0ix for poppy and soraka in their device trees respectively. BUG=b:36630881 BRANCH=none TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations). Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836 Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-22mainboard/google/poppy/variants/soraka: Update GPP_{D1,D2,B7} configFurquan Shaikh
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC in gpio table. BUG=b:62322846,b:62240755 Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20672 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-22mainboard/google/poppy/variants/soraka: Define separate gpio tablesFurquan Shaikh
Now that soraka is starting to deviate from the baseboard w.r.t. gpio settings, make a new copy of gpio table before we make any variant-specific changes in it. BUG=b:62240755,b:62322846 BRANCH=None TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio configuration before and after this change remains same. Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13mainboard/google/soraka: add wacom touchscreen supportWisley Chen
Add wacom touchscreen support. BUG=b:37007801, b:37265219 BRANCH=None TEST=manual testing on Soraka board to ensue that touchscreen works at boot and after suspend/resume. Change-Id: I0fbae4782c6442149cda57d23c61ed87546621bb Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/20476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12mb/google/soraka: Do not reset PMIC during sleepNaresh G Solanki
1. Due to reset signal, PMIC loses its internal register state. This causes PMIC to be in improper state after sleep. 2. The intent of reset signal is to reset internal state of PMIC (which happens once during power on), hence avoid asserting reset signal when not needed. 3. As per PMIC (TPS68470) datasheet, device can be kept in SLEEP mode when not in use to save max possible power. To fix the same, do not reset PMIC while entering sleep. By keeping PMIC in SLEEP mode, Power consumption is < 1uW (Typ) upto 3.63uW (Max). Refs: TPS68470 datasheet. Measured value: 0.66uW TEST= Build the firmware for Soraka & boot to OS. Do S3 resume & check whether PMIC internal registers state are preserved. Change-Id: I93ce4d76b0376b64ae6d1067aca0fd7467af3582 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01mainboards: Remove unused EC event for thermal overloadDuncan Laurie
The Chrome EC event for "thermal overload" was never implemented and is being repurposed as the EC event mask is out of free bits. Remove this from the boards that were enabling it. BUG=b:36024430 TEST=build coreboot for affected boards Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27mainboard/google/soraka: Update VR config settingsRajneesh Bhardwaj
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:62063434 BRANCH=none TEST=Build and boot soraka. Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27 Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: G Naveen <naveen.g@intel.com> Reviewed-on: https://review.coreboot.org/20309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27mb/google/soraka: Remove MPS IMVP8 workaroundRajneesh Bhardwaj
Soraka uses MPS2949 IMVP8 controller and does not need the VR workaroud similar to Eve. BUG=None TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power mode in S3 and S0ix by measuring power. Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/20255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27mainboard/google/poppy: Update world facing camera sensorV Sowmya
Update the world facing camera sensor to OV13858 and also add delay of 5ms after xshutdown rising which indicates system ready status. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27mainboard/google/poppy: Add clock frequency for camera sensorsV Sowmya
Add clock frequency property into _DSD ACPI object and set it to 19.2MHz for camera sensors. Upstream camera kernel has added a check for clock frequency in sensor probe function and without this property sensor probe fails. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20294 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-20mb/google/poppy: Add camera devices power sequencing through ACPI power ↵V Sowmya
resources This patch controls the camera devices power through ACPI power resource. * Add Opregions for PMIC, * TI_PMIC_POWER_OPREGION * TI_PMIC_VR_VAL_OPREGION * TI_PMIC_CLK_OPREGION * TI_PMIC_CLK_FREQ_OPREGION * Add power resources for sensors and VCM, * OVTH for CAM0 * OVFI for CAM1 * VCMP for VCM * Implement _ON and _OFF methods for sensor and VCM module's power on and power off sequences. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/20054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20mb/google/poppy: Configure ports and endpoints for sensor and CIO2 devicesV Sowmya
Bind the camera sensor and CIO2 devices through the ports and endpoints configuration available in _DSD ACPI object. * Port represents an interface in a device. * Endpoint represents a connection to that interface. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19mb/google/poppy: Add MIPI camera support.V Sowmya
This patch adds mipi_camera.asl, * Add TPS68470 PMIC related ACPI objects. * Add OV cameras related ACPI objects. * Add Dongwoon AF DAC related ACPI objects. * SSDB: Sensor specific database for camera sensor. * CAMD: ACPI object to specify the camera device type. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19mainboard/google/{poppy,soraka}: Remove MIPI camera support from devicetree.cbV Sowmya
Remove MIPI camera related register entries from devicetree.cb. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy and soraka. Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/19619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 18:50:12 +0000