skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI

Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 27 insertions, 27 deletions

diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c
index e74e4afcf6..90a161126d 100644
--- a/src/mainboard/google/poppy/variants/baseboard/gpio.c
+++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c
@@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = {
 	/* C5  : SML0ALERT# ==> NC */
 	PAD_CFG_NC(GPP_C5),
 	/* C6  : SM1CLK ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
 	/* C7  : SM1DATA ==> NC */
 	PAD_CFG_NC(GPP_C7),
 	/* C8  : UART0_RXD ==> FP_INT */
@@ -147,13 +147,13 @@ static const struct pad_config gpio_table[] = {
 	/* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
 	PAD_CFG_GPO(GPP_C11, 0, DEEP),
 	/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
-	PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
 	/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
-	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
 	/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
-	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
 	/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
-	PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
 	/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
@@ -176,14 +176,14 @@ static const struct pad_config gpio_table[] = {
 	/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
 	PAD_CFG_GPO(GPP_C22, 0, DEEP),
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* D0  : SPI1_CS# ==> NC */
 	PAD_CFG_NC(GPP_D0),
 	/* D1  : SPI1_CLK ==> PEN_IRQ_L */
 	PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),
 	/* D2  : SPI1_MISO ==> PEN_PDCT_L */
-	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP),
 	/* D3  : SPI1_MOSI ==> NC */
 	PAD_CFG_NC(GPP_D3),
 	/* D4  : FASHTRIG ==> NC */
@@ -197,7 +197,7 @@ static const struct pad_config gpio_table[] = {
 	/* D8  : ISH_I2C1_SCL ==> NC */
 	PAD_CFG_NC(GPP_D8),
 	/* D9  : ISH_SPI_CS# ==> HP_IRQ_GPIO */
-	PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),
 	/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
 	PAD_CFG_GPO(GPP_D10, 1, DEEP),
 	/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
@@ -258,7 +258,7 @@ static const struct pad_config gpio_table[] = {
 	/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
 	PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
 	/* E15 : DDPD_HPD2 ==> SD_CD# */
-	PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),
 	/* E16 : DDPE_HPD3 ==> NC(TP244) */
 	PAD_CFG_NC(GPP_E16),
 	/* E17 : EDP_HPD */
@@ -278,13 +278,13 @@ static const struct pad_config gpio_table[] = {
 
 	/* The next 4 pads are for bit banging the amplifiers, default to I2S */
 	/* F0  : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
-	PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
 	/* F1  : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
-	PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
 	/* F2  : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
-	PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
 	/* F3  : I2S2_RXD */
-	PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 	/* F4  : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
 	PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
 	/* F5  : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
@@ -396,7 +396,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* E0  : SATAXPCI0 ==> H1_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c
index cd1258db95..92f866f399 100644
--- a/src/mainboard/google/poppy/variants/soraka/gpio.c
+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c
@@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = {
 	/* C5  : SML0ALERT# ==> NC */
 	PAD_CFG_NC(GPP_C5),
 	/* C6  : SM1CLK ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
 	/* C7  : SM1DATA ==> NC */
 	PAD_CFG_NC(GPP_C7),
 	/* C8  : UART0_RXD ==> FP_INT */
@@ -145,13 +145,13 @@ static const struct pad_config gpio_table[] = {
 	/* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
 	PAD_CFG_GPO(GPP_C11, 0, DEEP),
 	/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
-	PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
 	/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
-	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
 	/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
-	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
 	/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
-	PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
 	/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
@@ -174,7 +174,7 @@ static const struct pad_config gpio_table[] = {
 	/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
 	PAD_CFG_GPO(GPP_C22, 0, DEEP),
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* D0  : SPI1_CS# ==> NC */
 	PAD_CFG_NC(GPP_D0),
@@ -195,7 +195,7 @@ static const struct pad_config gpio_table[] = {
 	/* D8  : ISH_I2C1_SCL ==> NC */
 	PAD_CFG_NC(GPP_D8),
 	/* D9  : ISH_SPI_CS# ==> HP_IRQ_GPIO */
-	PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),
 	/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
 	PAD_CFG_GPO(GPP_D10, 1, DEEP),
 	/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
@@ -256,7 +256,7 @@ static const struct pad_config gpio_table[] = {
 	/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
 	PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
 	/* E15 : DDPD_HPD2 ==> SD_CD# */
-	PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),
 	/* E16 : DDPE_HPD3 ==> NC(TP244) */
 	PAD_CFG_NC(GPP_E16),
 	/* E17 : EDP_HPD */
@@ -276,13 +276,13 @@ static const struct pad_config gpio_table[] = {
 
 	/* The next 4 pads are for bit banging the amplifiers, default to I2S */
 	/* F0  : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
-	PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
 	/* F1  : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
-	PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
 	/* F2  : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
-	PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
 	/* F3  : I2S2_RXD */
-	PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 	/* F4  : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
 	PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
 	/* F5  : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
@@ -397,7 +397,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* E0  : SATAXPCI0 ==> H1_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),