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Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.
Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens/digitizers.
This removes non-present devices from the SSDT and relieves the OS of
the burden of probing.
BUG=b:121309055
TEST=build/boot Windows/linux on all poppy variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: Iee01dac943b6c2955f7af42ce0e9395fc609682f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70920
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For touchscreens/digitizers on poppy variants, drive the enable
GPIO high and hold in reset in romstage, then release from reset in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens/digitizers during ACPI SSDT generation (enabled in a
subsequent commit).
TEST=tested with the rest of patch train
Change-Id: I90ac4f09c343a28328f7d30254f0448cbe0c78b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The touchscreen reset GPIO is configured as PAD_CFG_TERM_GPO with an
internal pull-down, which puts it in a state of contention when the
reset pin is released / set to high. Fix this by changing the reset
GPIO to PAD_CFG_GPO like all other poppy variants use for the
touchscreen reset.
TEST=build/boot nocturne, touchscreen still works.
Change-Id: I1ad4bb9d4194485990f54ffa7bae05f5c9a39deb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With xDCI enabled, the right USB-C port does not work for USB data.
Additionally, it was disabled in stock ChromeOS firmware.
TEST=build/boot rammus, confirm right USB-C port works for booting,
under OS in Windows/Linux.
Change-Id: Ie343577d772563fa7d432b62aa8faa41d760102a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on nami, verify all touchpad
functions work correctly.
Change-Id: I0611da8bbea41565e603a1a1b7cc20226ba21c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309.
Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514
codecs to program the render and feedback slot numbers as appropriate.
TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify
audio functional with both Google project campfire drivers as well as
coolstar's AVS audio drivers.
Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
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Add a hook to allow a variant finalize to be called at the end of
ramstage.
BUG=b:245954151
TEST=Builds successfully
Change-Id: I00c091051e3499ca94b286d7fbe0a7a8bd38e635
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70319
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also sort includes.
Change-Id: Iccb7f28a2c913ae0983bf224a03610d7fdd13c68
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add the 'detect' flag to the Elan touchpad, so coreboot can determine
which touchpad type is present at runtime and generate the correct
ACPI entry for it (the Synaptics touchpad already has the flag).
Test: build/boot google/nami, verify touchpad works under Linux/Windows
Change-Id: I437d1d470552d55496dfe611f441331127c64250
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Historically, ChromeOS devices have worked around the problem of OEMs
using several different parts for touchpads/touchscreens by using a
ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
to indicate that the device may or may not be present, and that the
driver should probe to confirm device presence.
Since c636142b, coreboot now supports detection for i2c devices at
runtime when creating the device entries for the ACPI/SSDT tables,
rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
in the tree from using the 'probed' flag to the 'detect' flag.
Touchscreens require more involved power sequencing, which will be done
at some future time, after which they will switch over as well.
TEST: build/boot at least one variant for each baseboard in the tree.
Verify touchpad works under Linux and Windows. Verify only a single
touchpad device is present in the ACPI tables.
Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I088e514271b785e59907b0271eb89727ae1e7c05
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
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Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.
Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.
Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Clang does not seem to work with 'fall through' in comments.
Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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All Skylake mainboards use the default value for the setting `SataMode`.
Thus, drop it from their devicetree.
Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016.
This relands commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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It's commented in <types.h> that it shall provide <commonlib/helpers.h>.
Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.
Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy
boards only enable UART 0 because it's function 0 of PCI device 30, and
the PCI specification requires that function 0 of multifunction devices
be implemented if other functions are implemented as well.
Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b
(mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by
using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the
SerialIO device. This way, it remains enabled and the GPIO settings will
not be overwritten by FSP.
However, not all variants do this, but use some UART 0 pads as GPIOs. To
prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the
variants.
Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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All Atlas devices have the touchscreen controller, so probing for its
presence is unnecessary. Removing the probe requirement allows the
touchscreen ACPI device in Linux to re-enumerate when rebinding its
I2C adapter device.
Without this change, after rebinding the touchscreen's I2C adapter
device using sysfs the touchscreen ACPI and HID devices are absent, and
the touchscreen is unresponsive.
With this change, the touchscreen ACPI and HID devices are re-created
after rebinding its I2C adapter device, and the touchscreen becomes
responsive again.
BUG=b:177350937
TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds
with Linux 4.4 and 5.4.
Built new AP FW from Atlas Chrome OS firmware branch with this change
applied. Tested shipping RO + new RW, and new RO + new RW.
Test sequence:
1) Boot DUT, verify basic touchscreen functionality.
2) $ cd /sys/bus/platform/drivers/i2c_designware
3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1
4) $ echo i2c_designware.0 > unbind
5) Verify touchscreen is unresponsive (as expected after unbind).
6) $ ls -ld i2c_designware.0
ls: cannot access 'i2c_designware.0': No such file or directory
7) $ echo i2c_designware.0 > bind
*** Without this change: ***
8) Touchscreen remains unresponsive.
9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}}
ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory
lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6
*** With this change: ***
8) Touchscreen is functional again.
9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1
Signed-off-by: Matthew Blecker <matthewb@chromium.org>
Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: I411f4f2c237a9e2d39038ee30f2957698ee053bd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Replace `3` with `SaGv_Enabled`, which has the same value.
Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.
This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.
Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch overrides the get_wifi_sar_cbfs_filename()
to return different sar table according to the sku id.
BUG=b:173465272
TEST=checked bios log and the correct sar table was loaded.
Change-Id: Ia30d760b1a029197d470818c73bfd2c00514652d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.
Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml
BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find /sys/firmware/acpi/tables/ -type f) ; do
f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
{
Package (0x02)
{
"semtech,cs0-ground",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
Package (0x02)
{
"semtech,proxraw-strength",
Zero
},
Package (0x02)
{
"semtech,avg-pos-strength",
0x0200
},
Package (0x02)
{
"semtech,combined-sensors",
Package (0x03)
{
Zero,
One,
0x02
}
},
Package (0x02)
{
"semtech,resolution",
"finest"
}
}
Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50321
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated 'build/dsdt.dsl' are identical.
Change-Id: I4f8b77b3f196ca51346bb7932a40875c4dd5d2a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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|
There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.
Always ensure that values don't overflow by applying appropriate masks.
The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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On commit 64c03e3c ("mb/google/poppy: Fix race condition in acpi"),
we introduced a new Power Resource common to all the camera modules,
in order to resolve a race condition when both modules were in use
(e.g. during startup).
The nautilus variant also used the Power Supply I2C2.PMIC.OVTH, which
requires the new common PR, but the new dependency was not added.
Depend on the new Camera Common Power Resource.
Fixes: 64c03e3c ("mb/google/poppy: Fix race condition in acpi")
BRANCH=poppy
BUG=b:174941580
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Change-Id: Ifa6c70b7c02aec0112189eca573e76e53175d70d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
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Newer kernels can re-schedule new acpi command calls during a Sleep().
This causes that the following trace fails to detect the cameras:
[ 15.764725] drivers/acpi/power.c:358 Power resource [OVFI] turned on start
[ 15.772180] drivers/acpi/power.c:358 Power resource [OVTH] turned on start
[ 15.834970] drivers/acpi/power.c:362 Power resource [OVFI] turned on start
[ 15.852456] drivers/acpi/power.c:415 Power resource [OVFI] turned off start
[ 15.955987] drivers/acpi/power.c:420 Power resource [OVFI] turned off end
ERROR!!
[ 16.030896] drivers/acpi/power.c:362 Power resource [OVTH] turned on end
Which can be triggered more frequently if the Sleep() commands in OVTH
_ON Method are increased.
To avoid the race condition, we create a new Power Resource that
handles the common resources of both cameras and make both cameras
depend on that resource. This also simplifies the acpi table by removing
a Mutex.
BRANCH=poppy
BUG=b:171955583
TEST=while true; do if ssh $DUT "dmesg | grep \"failed to find sensor\" "; then break; fi; ssh $DUT reboot; sleep 30 ; done
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Change-Id: I25df0225699759c1828b8791c5bdee66529858a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48631
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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|
The value for this setting is not used anywhere. Drop it.
Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
"Die()" needs <console/console.h>.
Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.
Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.
Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ida1b1d05b39e67a9eba3bfaecca37f38821a438b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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|
This patch makes Atlas resume from S0ix by AC plug and unplug.
BUG=b:165328935
BRANCH=atlas
TEST=Put Atlas in suspend. Wake it up by AC plug.
TEST=Put Atlas in suspend. Wake it up by AC unplug.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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|
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).
Thus, drop the setting from all devicetrees.
Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
1. Add new SPD file, "samsung_dimm_K4E8E324ED-EGCG.spd.hex".
2. Add SPD support in Rammus memory table, as follows:
SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110
SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111
BUG=b:166576463
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Convert 0X -> 0x
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.
Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.
All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.
Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.
All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.
Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.
Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.
I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.
Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.
I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.
Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.
Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.
Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.
BUG=b:159942427
Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39
Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Idfc7a5713e231c4756b5faca8984c6598fe1e65a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie7eb4c43178acff2dc5ff7c685e71990d8f353c9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add HID field in max98357a_config and allow mainboards to set it.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This patch creates a new commonlib/bsd subdirectory with a similar
purpose to the existing commonlib, with the difference that all files
under this subdirectory shall be licensed under the BSD-3-Clause license
(or compatible permissive license). The goal is to allow more code to be
shared with libpayload in the future.
Initially, I'm going to move a few files there that have already been
BSD-licensed in the existing commonlib. I am also exracting most
contents of the often-needed <commonlib/helpers.h> as long as they have
either been written by me (and are hereby relicensed) or have an
existing equivalent in BSD-licensed libpayload code. I am also
relicensing <commonlib/compression.h> (written by me) and
<commonlib/compiler.h> (same stuff exists in libpayload).
Finally, I am extracting the cb_err error code definitions from
<types.h> into a new BSD-licensed header so that future commonlib/bsd
code can build upon a common set of error values. I am making the
assumption here that the enum constants and the half-sentence fragments
of documentation next to them by themselves do not meet the threshold of
copyrightability.
Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add Kconfig, panel delays extracted from VBT (and confirmed by Linux)
Test: build/boot Atlas with libgfxinit and Tianocore payload
Change-Id: I94c227cd4f020db719bf81118d983493752bb00f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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On nocturne, the VBT specifies that the native panel resolution
(3000x2000) is to be used by FSP/GOP init, which makes payload
and grub menus extremely difficult to read. Change the default
POST resolution specified by the VBT to 1500x1000 instead
(200% scaling) which is much more legible.
Test: build/boot nocturne with GOP init and Tianocore payload,
observe menu text is actually readable.
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I767a2b8319c7673e3460acfad534140409bf1d57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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configuration
The methods generally tested OP region settings and only changed them if
they were not in their desired values. Instead, assign them directly
without checking them.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mutex is only used in one method and that method is serialised. Remove
the mutex.
BUG=chromium:959232
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36745
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In particular:
- Set voltage before enabling regulators
- Enable regulators and the clock without any sleeping in between. There's
no need to wait there.
- Sleep 1 ms in order to wait for regulator voltages settling before
lifting xshutdown.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In particular:
- Enable regulators *after* configuring the voltage
- Allow 1 ms for the voltages to settle
- Enable clock after powering on regulators
- Remove extra delays between enabling things. The sensor requires 8192
clock cycles after the reset is lifted before I²C access, so 1 ms is
enough.
- Make the delay after lifting xshutdown 10 ms. This guarantees that
streaming will only start once the sensor has had enough time to settle
after lifting the reset.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The PMIC opregion is used to change the direction of two GPIOs for I²C
daisy chain operation. Do this after the PMIC is powered on, not before.
BUG=chromium:959232
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The pull direction is used to determine the initial state of the pin. If
no pull direction is specified, the pin will remain as input. Fix this.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I1158bc8aaa447b223e8ce25d808348e758de28c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add libgfxinit support for rammus. Use panel init values from VBT.
Test: build/boot rammus with libgfxinit and Tianocore payload
Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add VBT files for Atlas, Nocturne, Rammus, and Soraka variants.
Extracted from ChromeOS recovery images for the respective boards.
Select INTEL_GMA_HAVE_VBT for all variants except Poppy, since
it doesn't have a VBT (or a recovery image from which to extract one).
Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change removes an inversion of GPP_D17 that caused the
device to get stuck in a reboot loop because the kernel was crashing
within the first couple seconds of kernel boot.
BUG=b:142515200
BRANCH=none
TEST=Flash and boot nocturne, verify boot is stable and that device
doesn't reboot after jumping into kernel, and that it passes the
'tast -verbose run <ip> hardware.SensorRing' test.
Change-Id: Ia1408ef6ea92f6b31a9f3eee8720954af3a7c382
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35967
Reviewed-by: Yicheng Li <yichengli@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add data.vbt and modify Kconfig appropriately;
allows use of FSP/GOP display init.
VBT extracted from stock ChromeOS firmware.
Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.
Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as
EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979
BRANCH=none
TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage",
flash & boot nocturne in dev mode, verify that volume up and down
buttons work in the dev screen and that the device boots properly into
the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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add sku ids of bard/ekko
BUG=b:139886622
TEST=emerge-nami coreboot
Change-Id: Iabc3d587c3839e4a3121cea8504c50e2dc4f9699
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35115
Reviewed-by: Vincent Wang <vwang@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch ensures skylake soc is using common thermal code
from intel common block.
TEST=Build and boot soraka
Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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add two sku ids of bard:
0x1009CE0
0x1009CE2
BUG=b:137892804
TEST=emerge-nami coreboot
Change-Id: I299ccb36739d83e38f37e0b2cbba44c34343c975
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
We would like to wake nocturne up in suspend from an MKBP event. On
Nocturne, MKBP events are notified to the host via a GPIO from the EC,
EC_INT_L. However, the AP cannot wake from suspend from this GPIO.
Therefore, we'll use the host event interface to wake the system
instead.
This commit simply enables MKBP events to wake the system in suspend.
BUG=chromium:786721
BRANCH=firmware-nocturne-10984.B
TEST=Build and flash nocturne, generate MKBP events on the EC and verify
that the system wakes up in suspend.
Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I53324603c9ece1334c6e09d51338084166f7a585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The temperature delta between on-board thermistor and
surface temp change, so update DPTF parameter accordingly.
BUG=b:113101335
TEST=Tested in thermal chamber by thermal team.
See comment 148 / 153 in the bug.
Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
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